DE69511628D1 - Pulserzeugung - Google Patents
PulserzeugungInfo
- Publication number
- DE69511628D1 DE69511628D1 DE69511628T DE69511628T DE69511628D1 DE 69511628 D1 DE69511628 D1 DE 69511628D1 DE 69511628 T DE69511628 T DE 69511628T DE 69511628 T DE69511628 T DE 69511628T DE 69511628 D1 DE69511628 D1 DE 69511628D1
- Authority
- DE
- Germany
- Prior art keywords
- pulse generation
- pulse
- generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9411602A GB9411602D0 (en) | 1994-06-09 | 1994-06-09 | Pulse generation |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69511628D1 true DE69511628D1 (de) | 1999-09-30 |
DE69511628T2 DE69511628T2 (de) | 1999-12-09 |
Family
ID=10756491
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69519526T Expired - Fee Related DE69519526T2 (de) | 1994-06-09 | 1995-06-02 | Pulserzeugung |
DE69511628T Expired - Fee Related DE69511628T2 (de) | 1994-06-09 | 1995-06-02 | Pulserzeugung |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69519526T Expired - Fee Related DE69519526T2 (de) | 1994-06-09 | 1995-06-02 | Pulserzeugung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5684424A (de) |
EP (2) | EP0877486B1 (de) |
JP (1) | JPH08181586A (de) |
DE (2) | DE69519526T2 (de) |
GB (1) | GB9411602D0 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3410922B2 (ja) * | 1996-04-23 | 2003-05-26 | 株式会社東芝 | クロック制御回路 |
JP3085258B2 (ja) * | 1997-09-10 | 2000-09-04 | 日本電気株式会社 | クロック信号分配回路 |
US6147526A (en) * | 1997-12-23 | 2000-11-14 | Texas Instruments Incorporated | Ripple regulator with improved initial accuracy and noise immunity |
KR100284741B1 (ko) * | 1998-12-18 | 2001-03-15 | 윤종용 | 로컬클럭 신호 발생회로 및 방법, 내부클럭신호 발생회로 및방법,이를 이용한 반도체 메모리 장치 |
US6271682B1 (en) * | 1999-09-01 | 2001-08-07 | Micron Technology, Inc. | Method and apparatus for high-speed edge-programmable timing signal generator |
JP3495311B2 (ja) * | 2000-03-24 | 2004-02-09 | Necエレクトロニクス株式会社 | クロック制御回路 |
JP3498069B2 (ja) * | 2000-04-27 | 2004-02-16 | Necエレクトロニクス株式会社 | クロック制御回路および方法 |
US6847582B2 (en) * | 2003-03-11 | 2005-01-25 | Micron Technology, Inc. | Low skew clock input buffer and method |
US7324403B2 (en) * | 2004-09-24 | 2008-01-29 | Intel Corporation | Latency normalization by balancing early and late clocks |
KR100810402B1 (ko) * | 2005-09-15 | 2008-03-04 | 키몬다 아게 | 입력 신호에 대해 사전 결정된 위상 시프트를 갖는 출력신호를 생성하는 방법 및 장치 |
JP2009152822A (ja) * | 2007-12-20 | 2009-07-09 | Spansion Llc | 記憶装置 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2703431C2 (de) * | 1977-01-28 | 1986-09-18 | Robert Bosch Gmbh, 7000 Stuttgart | Zündanlage für Brennkraftmaschinen |
US4404481A (en) * | 1980-10-20 | 1983-09-13 | Matsushita Electric Industrial Co., Ltd. | Capacitance to voltage conversion apparatus |
US4634984A (en) * | 1985-04-18 | 1987-01-06 | Rca Corporation | Duration-sensitive digital signal gate |
JPH01251738A (ja) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | スタンダードセル |
US4868522A (en) * | 1988-12-13 | 1989-09-19 | Gazelle Microcircuits, Inc. | Clock signal distribution device |
US4970418A (en) * | 1989-09-26 | 1990-11-13 | Apple Computer, Inc. | Programmable memory state machine for providing variable clocking to a multimode memory |
US5059818A (en) * | 1990-06-01 | 1991-10-22 | Advanced Micro Devices, Inc. | Self-regulating clock generator |
JPH04205326A (ja) * | 1990-11-30 | 1992-07-27 | Fujitsu Ltd | 並列計算機のクロック発生方式 |
US5214319A (en) * | 1991-05-28 | 1993-05-25 | Motorola, Inc. | Monotonic pulse detector |
JPH0512223A (ja) * | 1991-07-05 | 1993-01-22 | Fujitsu Ltd | 並列計算機のクロツク系 |
JPH0566851A (ja) * | 1991-09-10 | 1993-03-19 | Fujitsu Ltd | 複数の回路ブロツクへのタイミング信号付与方法 |
GB9203587D0 (en) * | 1992-02-20 | 1992-04-08 | Motorola Inc | Bus format detector |
US5444405A (en) * | 1992-03-02 | 1995-08-22 | Seiko Epson Corporation | Clock generator with programmable non-overlapping clock edge capability |
JP3517237B2 (ja) * | 1992-03-06 | 2004-04-12 | ラムバス・インコーポレーテッド | 同期バス・システムおよびそのためのメモリ装置 |
US5396129A (en) * | 1992-05-25 | 1995-03-07 | Matsushita Electronics Corporation | Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape |
DE4242201A1 (de) * | 1992-12-15 | 1994-06-16 | Philips Patentverwaltung | Schaltungsanordnung zum Verzögern eines Nutzsignals |
US5394020A (en) * | 1992-12-30 | 1995-02-28 | Zenith Electronics Corporation | Vertical ramp automatic amplitude control |
US5355035A (en) * | 1993-01-08 | 1994-10-11 | Vora Madhukar B | High speed BICMOS switches and multiplexers |
JP3194314B2 (ja) * | 1993-04-28 | 2001-07-30 | ソニー株式会社 | 同期型回路 |
US5510739A (en) * | 1994-03-28 | 1996-04-23 | Motorola, Inc. | Circuit and method for enhancing logic transitions appearing on a line |
-
1994
- 1994-06-09 GB GB9411602A patent/GB9411602D0/en active Pending
-
1995
- 1995-06-02 DE DE69519526T patent/DE69519526T2/de not_active Expired - Fee Related
- 1995-06-02 DE DE69511628T patent/DE69511628T2/de not_active Expired - Fee Related
- 1995-06-02 EP EP98202717A patent/EP0877486B1/de not_active Expired - Lifetime
- 1995-06-02 EP EP95303781A patent/EP0687069B1/de not_active Expired - Lifetime
- 1995-06-06 US US08/468,726 patent/US5684424A/en not_active Expired - Lifetime
- 1995-06-08 JP JP7141870A patent/JPH08181586A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE69511628T2 (de) | 1999-12-09 |
EP0877486A1 (de) | 1998-11-11 |
EP0877486B1 (de) | 2000-11-29 |
DE69519526D1 (de) | 2001-01-04 |
EP0687069A1 (de) | 1995-12-13 |
EP0687069B1 (de) | 1999-08-25 |
DE69519526T2 (de) | 2001-05-17 |
JPH08181586A (ja) | 1996-07-12 |
GB9411602D0 (en) | 1994-08-03 |
US5684424A (en) | 1997-11-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |