DE69500586D1 - Herstellungsverfahren für ein Halbleiter-Bauelement zur Speicherung mehrerer Zustände - Google Patents
Herstellungsverfahren für ein Halbleiter-Bauelement zur Speicherung mehrerer ZuständeInfo
- Publication number
- DE69500586D1 DE69500586D1 DE69500586T DE69500586T DE69500586D1 DE 69500586 D1 DE69500586 D1 DE 69500586D1 DE 69500586 T DE69500586 T DE 69500586T DE 69500586 T DE69500586 T DE 69500586T DE 69500586 D1 DE69500586 D1 DE 69500586D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor device
- manufacturing process
- storing multiple
- multiple states
- states
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3768794A JPH07226446A (ja) | 1994-02-12 | 1994-02-12 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69500586D1 true DE69500586D1 (de) | 1997-10-02 |
DE69500586T2 DE69500586T2 (de) | 1998-02-05 |
Family
ID=12504495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69500586T Expired - Lifetime DE69500586T2 (de) | 1994-02-12 | 1995-02-10 | Herstellungsverfahren für ein Halbleiter-Bauelement zur Speicherung mehrerer Zustände |
Country Status (6)
Country | Link |
---|---|
US (2) | US5629548A (de) |
EP (1) | EP0667644B1 (de) |
JP (1) | JPH07226446A (de) |
KR (1) | KR950025987A (de) |
DE (1) | DE69500586T2 (de) |
TW (1) | TW275149B (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5693551A (en) * | 1995-09-19 | 1997-12-02 | United Microelectronics, Corporation | Method for fabricating a tri-state read-only memory device |
JP3634086B2 (ja) | 1996-08-13 | 2005-03-30 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置の作製方法 |
JP4014676B2 (ja) | 1996-08-13 | 2007-11-28 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置およびその作製方法 |
JP4103968B2 (ja) | 1996-09-18 | 2008-06-18 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置 |
US6590230B1 (en) | 1996-10-15 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP4104701B2 (ja) * | 1997-06-26 | 2008-06-18 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US6686623B2 (en) | 1997-11-18 | 2004-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and electronic apparatus |
JP4236722B2 (ja) * | 1998-02-05 | 2009-03-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6238982B1 (en) * | 1999-04-13 | 2001-05-29 | Advanced Micro Devices | Multiple threshold voltage semiconductor device fabrication technology |
US6724037B2 (en) * | 2000-07-21 | 2004-04-20 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and semiconductor device |
US6683337B2 (en) * | 2001-02-09 | 2004-01-27 | Micron Technology, Inc. | Dynamic memory based on single electron storage |
KR100650867B1 (ko) * | 2005-12-29 | 2006-11-28 | 동부일렉트로닉스 주식회사 | 협채널 금속 산화물 반도체 트랜지스터 |
US20120244668A1 (en) * | 2011-03-25 | 2012-09-27 | Jeesung Jung | Semiconductor devices with layout controlled channel and associated processes of manufacturing |
US8742481B2 (en) * | 2011-08-16 | 2014-06-03 | Micron Technology, Inc. | Apparatuses and methods comprising a channel region having different minority carrier lifetimes |
US10069015B2 (en) | 2016-09-26 | 2018-09-04 | International Business Machines Corporation | Width adjustment of stacked nanowires |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4272830A (en) * | 1978-12-22 | 1981-06-09 | Motorola, Inc. | ROM Storage location having more than two states |
US4317273A (en) * | 1979-11-13 | 1982-03-02 | Texas Instruments Incorporated | Method of making high coupling ratio DMOS electrically programmable ROM |
US4395725A (en) * | 1980-10-14 | 1983-07-26 | Parekh Rajesh H | Segmented channel field effect transistors |
JPS59148360A (ja) * | 1983-02-14 | 1984-08-25 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
US4811066A (en) * | 1987-10-19 | 1989-03-07 | Motorola, Inc. | Compact multi-state ROM cell |
US5168465A (en) * | 1988-06-08 | 1992-12-01 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
JPH03185758A (ja) * | 1989-12-14 | 1991-08-13 | Sharp Corp | 半導体装置の製造方法 |
IT1240669B (it) * | 1990-02-27 | 1993-12-17 | Sgs Thomson Microelectronics | Procedimento di programmazione atto a definire almeno quattro differenti livelli di corrente in una cella di memoria rom |
US5285069A (en) * | 1990-11-21 | 1994-02-08 | Ricoh Company, Ltd. | Array of field effect transistors of different threshold voltages in same semiconductor integrated circuit |
JPH0555566A (ja) * | 1991-08-28 | 1993-03-05 | Nec Corp | 半導体装置 |
US5306657A (en) * | 1993-03-22 | 1994-04-26 | United Microelectronics Corporation | Process for forming an FET read only memory device |
-
1994
- 1994-02-12 JP JP3768794A patent/JPH07226446A/ja active Pending
-
1995
- 1995-02-10 US US08/386,477 patent/US5629548A/en not_active Expired - Fee Related
- 1995-02-10 EP EP95101831A patent/EP0667644B1/de not_active Expired - Lifetime
- 1995-02-10 DE DE69500586T patent/DE69500586T2/de not_active Expired - Lifetime
- 1995-02-10 KR KR1019940002480A patent/KR950025987A/ko not_active Application Discontinuation
- 1995-02-15 TW TW084101364A patent/TW275149B/zh not_active IP Right Cessation
-
1996
- 1996-12-20 US US08/771,287 patent/US5885872A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5629548A (en) | 1997-05-13 |
KR950025987A (ko) | 1995-09-18 |
US5885872A (en) | 1999-03-23 |
TW275149B (de) | 1996-05-01 |
EP0667644A1 (de) | 1995-08-16 |
JPH07226446A (ja) | 1995-08-22 |
DE69500586T2 (de) | 1998-02-05 |
EP0667644B1 (de) | 1997-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |