DE69424830D1 - Halbleiteranordnung mit geringem Flächenbedarf der Verbindungen innerhalb und ausserhalb des Datenleitungsgebietes - Google Patents

Halbleiteranordnung mit geringem Flächenbedarf der Verbindungen innerhalb und ausserhalb des Datenleitungsgebietes

Info

Publication number
DE69424830D1
DE69424830D1 DE69424830T DE69424830T DE69424830D1 DE 69424830 D1 DE69424830 D1 DE 69424830D1 DE 69424830 T DE69424830 T DE 69424830T DE 69424830 T DE69424830 T DE 69424830T DE 69424830 D1 DE69424830 D1 DE 69424830D1
Authority
DE
Germany
Prior art keywords
outside
data line
semiconductor arrangement
connections inside
small area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69424830T
Other languages
English (en)
Other versions
DE69424830T2 (de
Inventor
Hisao Harigai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69424830D1 publication Critical patent/DE69424830D1/de
Application granted granted Critical
Publication of DE69424830T2 publication Critical patent/DE69424830T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69424830T 1993-07-30 1994-08-01 Halbleiteranordnung mit geringem Flächenbedarf der Verbindungen innerhalb und ausserhalb des Datenleitungsgebietes Expired - Fee Related DE69424830T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5207015A JP2718345B2 (ja) 1993-07-30 1993-07-30 半導体装置

Publications (2)

Publication Number Publication Date
DE69424830D1 true DE69424830D1 (de) 2000-07-13
DE69424830T2 DE69424830T2 (de) 2001-01-18

Family

ID=16532788

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424830T Expired - Fee Related DE69424830T2 (de) 1993-07-30 1994-08-01 Halbleiteranordnung mit geringem Flächenbedarf der Verbindungen innerhalb und ausserhalb des Datenleitungsgebietes

Country Status (5)

Country Link
US (1) US5583374A (de)
EP (1) EP0637083B1 (de)
JP (1) JP2718345B2 (de)
KR (1) KR0135237B1 (de)
DE (1) DE69424830T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763944A (en) * 1994-08-01 1998-06-09 Nec Corporation Semiconductor device having a reduced wiring area in and out of data path zone

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750741B2 (ja) * 1985-02-28 1995-05-31 株式会社東芝 半導体集積回路
JPH0650761B2 (ja) * 1986-08-12 1994-06-29 富士通株式会社 半導体装置
JPH0812882B2 (ja) * 1987-08-25 1996-02-07 富士通株式会社 半導体集積回路
JPH02155267A (ja) * 1988-12-07 1990-06-14 Mitsubishi Electric Corp 半導体集積回路装置
JPH02306659A (ja) * 1989-05-22 1990-12-20 Seiko Epson Corp 半導体装置
JPH03225697A (ja) * 1990-01-30 1991-10-04 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
US5583374A (en) 1996-12-10
EP0637083A1 (de) 1995-02-01
JPH0745709A (ja) 1995-02-14
JP2718345B2 (ja) 1998-02-25
KR0135237B1 (ko) 1998-04-22
DE69424830T2 (de) 2001-01-18
KR950004496A (ko) 1995-02-18
EP0637083B1 (de) 2000-06-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee