DE69416761D1 - Speicherschutzschaltung für EPROM - Google Patents
Speicherschutzschaltung für EPROMInfo
- Publication number
- DE69416761D1 DE69416761D1 DE69416761T DE69416761T DE69416761D1 DE 69416761 D1 DE69416761 D1 DE 69416761D1 DE 69416761 T DE69416761 T DE 69416761T DE 69416761 T DE69416761 T DE 69416761T DE 69416761 D1 DE69416761 D1 DE 69416761D1
- Authority
- DE
- Germany
- Prior art keywords
- eprom
- protection circuit
- memory protection
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Storage Device Security (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5255298A JPH0793223A (ja) | 1993-09-20 | 1993-09-20 | 記憶情報保護回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69416761D1 true DE69416761D1 (de) | 1999-04-08 |
DE69416761T2 DE69416761T2 (de) | 1999-09-02 |
Family
ID=17276834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69416761T Expired - Fee Related DE69416761T2 (de) | 1993-09-20 | 1994-09-20 | Speicherschutzschaltung für EPROM |
Country Status (4)
Country | Link |
---|---|
US (1) | US5506806A (de) |
EP (1) | EP0645774B1 (de) |
JP (1) | JPH0793223A (de) |
DE (1) | DE69416761T2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3487690B2 (ja) * | 1995-06-20 | 2004-01-19 | シャープ株式会社 | 不揮発性半導体記憶装置 |
US6396368B1 (en) | 1999-11-10 | 2002-05-28 | Hrl Laboratories, Llc | CMOS-compatible MEM switches and method of making |
US7217977B2 (en) * | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
US6815816B1 (en) * | 2000-10-25 | 2004-11-09 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
US6791191B2 (en) | 2001-01-24 | 2004-09-14 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations |
US7294935B2 (en) * | 2001-01-24 | 2007-11-13 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
US6459629B1 (en) * | 2001-05-03 | 2002-10-01 | Hrl Laboratories, Llc | Memory with a bit line block and/or a word line block for preventing reverse engineering |
US6740942B2 (en) * | 2001-06-15 | 2004-05-25 | Hrl Laboratories, Llc. | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
US6774413B2 (en) * | 2001-06-15 | 2004-08-10 | Hrl Laboratories, Llc | Integrated circuit structure with programmable connector/isolator |
US6897535B2 (en) | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
US6874069B2 (en) * | 2002-07-26 | 2005-03-29 | Silicon Storage Technology, Inc. | Microcontroller having an embedded non-volatile memory array with read protection for the array or portions thereof |
US7049667B2 (en) * | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
US6979606B2 (en) * | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
AU2003293540A1 (en) | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
US6879518B1 (en) * | 2003-11-21 | 2005-04-12 | Atmel Corporation | Embedded memory with security row lock protection |
JP2005166184A (ja) * | 2003-12-04 | 2005-06-23 | Sharp Corp | 半導体記憶装置 |
EP1603138A1 (de) | 2004-04-15 | 2005-12-07 | STMicroelectronics SA | Nichtflüchtiger Speicher mit Mittel zur Verfälschung der Auslese von Speicherzellen |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
US8168487B2 (en) * | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
US8871431B2 (en) | 2011-08-08 | 2014-10-28 | Timothy Gotsick | Laminated flexographic printing sleeves and methods of making the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6057597A (ja) * | 1983-09-08 | 1985-04-03 | Oki Electric Ind Co Ltd | プログラマブルrom |
JPS6128144A (ja) * | 1984-07-18 | 1986-02-07 | Matsushita Electric Ind Co Ltd | トレ−ス動作実行装置 |
JPS6157099A (ja) * | 1984-08-28 | 1986-03-22 | Matsushita Electric Ind Co Ltd | Eprom書き込み禁止回路 |
JP2842442B2 (ja) * | 1985-04-26 | 1999-01-06 | 株式会社日立製作所 | マイクロコンピュータ、不揮発性半導体記憶装置、ならびにその書込みおよび消去方法 |
US4744062A (en) * | 1985-04-23 | 1988-05-10 | Hitachi, Ltd. | Semiconductor integrated circuit with nonvolatile memory |
US4791612A (en) * | 1985-12-18 | 1988-12-13 | Fujitsu Limited | Data programming circuit for programmable read only memory device |
JPS62236053A (ja) * | 1986-04-07 | 1987-10-16 | Matsushita Electric Ind Co Ltd | Eeprom読み出し禁止回路 |
JPH02299039A (ja) * | 1989-05-12 | 1990-12-11 | Toshiba Corp | 半導体メモリ装置 |
JPH0520204A (ja) * | 1991-07-11 | 1993-01-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2632104B2 (ja) * | 1991-11-07 | 1997-07-23 | 三菱電機株式会社 | 不揮発性半導体記憶装置 |
US5381369A (en) * | 1993-02-05 | 1995-01-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device using a command control system |
-
1993
- 1993-09-20 JP JP5255298A patent/JPH0793223A/ja active Pending
-
1994
- 1994-09-20 EP EP94114821A patent/EP0645774B1/de not_active Expired - Lifetime
- 1994-09-20 US US08/309,028 patent/US5506806A/en not_active Expired - Fee Related
- 1994-09-20 DE DE69416761T patent/DE69416761T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0645774A2 (de) | 1995-03-29 |
JPH0793223A (ja) | 1995-04-07 |
US5506806A (en) | 1996-04-09 |
EP0645774B1 (de) | 1999-03-03 |
DE69416761T2 (de) | 1999-09-02 |
EP0645774A3 (de) | 1995-11-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |