DE69332817D1 - Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und Multiplikator - Google Patents
Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und MultiplikatorInfo
- Publication number
- DE69332817D1 DE69332817D1 DE69332817T DE69332817T DE69332817D1 DE 69332817 D1 DE69332817 D1 DE 69332817D1 DE 69332817 T DE69332817 T DE 69332817T DE 69332817 T DE69332817 T DE 69332817T DE 69332817 D1 DE69332817 D1 DE 69332817D1
- Authority
- DE
- Germany
- Prior art keywords
- multiplier
- logic circuit
- automatic design
- automatic
- design
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Complex Calculations (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4348269A JP2840169B2 (ja) | 1992-12-28 | 1992-12-28 | 論理回路の自動設計方法およびその装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69332817D1 true DE69332817D1 (de) | 2003-05-08 |
DE69332817T2 DE69332817T2 (de) | 2003-11-06 |
Family
ID=18395900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69332817T Expired - Fee Related DE69332817T2 (de) | 1992-12-28 | 1993-12-28 | Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und Multiplikator |
Country Status (5)
Country | Link |
---|---|
US (2) | US5530664A (de) |
EP (1) | EP0605885B1 (de) |
JP (1) | JP2840169B2 (de) |
KR (1) | KR970006408B1 (de) |
DE (1) | DE69332817T2 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2972498B2 (ja) * | 1993-09-02 | 1999-11-08 | 松下電器産業株式会社 | 論理回路の自動設計方法、そのシステム及びその装置並びに乗算器 |
JP2972540B2 (ja) * | 1994-03-24 | 1999-11-08 | 松下電器産業株式会社 | Lsi自動設計システム及びlsi自動設計方法 |
US5815422A (en) * | 1997-01-24 | 1998-09-29 | Vlsi Technology, Inc. | Computer-implemented multiplication with shifting of pattern-product partials |
US6718465B1 (en) * | 2000-02-25 | 2004-04-06 | The Research Foundation Of State University Of New York | Reconfigurable inner product processor architecture implementing square recursive decomposition of partial product matrices |
US6978426B2 (en) * | 2002-04-10 | 2005-12-20 | Broadcom Corporation | Low-error fixed-width modified booth multiplier |
US6971083B1 (en) | 2002-11-13 | 2005-11-29 | Altera Corporation | Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions |
US7395300B2 (en) * | 2004-01-27 | 2008-07-01 | Broadcom Corporation | System, and method for calculating product of constant and mixed number power of two |
US7380226B1 (en) * | 2004-12-29 | 2008-05-27 | Cadence Design Systems, Inc. | Systems, methods, and apparatus to perform logic synthesis preserving high-level specification |
US7912891B2 (en) * | 2005-12-09 | 2011-03-22 | Electronics And Telecommunications Research Institute | High speed low power fixed-point multiplier and method thereof |
US10289259B2 (en) | 2007-02-13 | 2019-05-14 | Visual Targeting Corporation | Method for defining a presentation format targetable to a demographic |
GB201111243D0 (en) * | 2011-06-30 | 2011-08-17 | Imagination Tech Ltd | Method and apparatus for use in the sysnthesis of lossy integer multipliers |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5164844A (de) * | 1974-12-03 | 1976-06-04 | Fujitsu Ltd | |
US4964056A (en) * | 1987-03-25 | 1990-10-16 | Hitachi, Ltd. | Automatic design system of logic circuit |
JP2877303B2 (ja) * | 1987-03-31 | 1999-03-31 | 株式会社東芝 | 集積回路の自動設計装置 |
JPH0315984A (ja) * | 1987-09-25 | 1991-01-24 | Matsushita Electric Ind Co Ltd | 機能記述変換方法と論理設計システム |
JP2506991B2 (ja) * | 1987-09-25 | 1996-06-12 | 松下電器産業株式会社 | 回路変換システムと回路変換方法と反転論理生成方法および論理設計システム |
KR920003908B1 (ko) * | 1987-11-19 | 1992-05-18 | 미쓰비시뎅끼 가부시끼가이샤 | 승산기(乘算器) |
JP2682142B2 (ja) * | 1989-06-14 | 1997-11-26 | 松下電器産業株式会社 | 乗算装置 |
FR2650088A1 (fr) * | 1989-07-18 | 1991-01-25 | Thomson Csf | Procede pour la generation de schemas logiques de circuits multiplieurs parametrables a decodeur de booth au moyen d'un ordinateur et circuits multiplieurs correspondants |
FR2656124A1 (fr) * | 1989-12-15 | 1991-06-21 | Philips Laboratoires Electro | Multiplieur serie programmable. |
JP2563663B2 (ja) * | 1990-08-20 | 1996-12-11 | 松下電器産業株式会社 | 論理設計処理装置およびタイミング調整方法 |
US5345393A (en) * | 1990-08-22 | 1994-09-06 | Matsushita Electric Industrial Co., Ltd. | Logic circuit generator |
US5351206A (en) * | 1992-11-12 | 1994-09-27 | Vlsi Technology, Inc. | Signed two's complement constant multiplier compiler |
-
1992
- 1992-12-28 JP JP4348269A patent/JP2840169B2/ja not_active Expired - Fee Related
-
1993
- 1993-12-20 KR KR1019930028580A patent/KR970006408B1/ko not_active IP Right Cessation
- 1993-12-28 US US08/174,450 patent/US5530664A/en not_active Expired - Lifetime
- 1993-12-28 EP EP93121019A patent/EP0605885B1/de not_active Expired - Lifetime
- 1993-12-28 DE DE69332817T patent/DE69332817T2/de not_active Expired - Fee Related
-
1996
- 1996-03-21 US US08/620,046 patent/US5703802A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69332817T2 (de) | 2003-11-06 |
EP0605885A2 (de) | 1994-07-13 |
EP0605885A3 (de) | 1995-05-10 |
US5703802A (en) | 1997-12-30 |
KR970006408B1 (ko) | 1997-04-28 |
EP0605885B1 (de) | 2003-04-02 |
KR940015785A (ko) | 1994-07-21 |
JP2840169B2 (ja) | 1998-12-24 |
US5530664A (en) | 1996-06-25 |
JPH06203098A (ja) | 1994-07-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69315090D1 (de) | Vorrichtung und verfahren zum einkapseln | |
DE69131922D1 (de) | Verfahren und Gerät zum Ausziehen von Aussenlinien | |
DE69333096D1 (de) | Vorrichtungen und Verfahren zum graphischen Zeichnen und Ausgabe | |
DE69329502D1 (de) | Verfahren zum Montieren von Chip-Bauteilen und Gerät dafür | |
DE4396373T1 (de) | Bindevorrichtung sowie Gerät und Verfahren zum Binden der Bindevorrichtung | |
DE69119787D1 (de) | Apherese verfahren und vorrichtung dafuer | |
DE69324309D1 (de) | Verfahren und Vorrichtung zum Orten und Folgen von Antwortgeräten | |
DE69430474D1 (de) | Verfahren und gerät zum verbinden von metallstücken | |
DE69411213D1 (de) | Verfahren und Vorrichtung zum Waschen von Substraten | |
DE69308361D1 (de) | Halbleiteranordnung und Verfahren zum Zusammensetzen derselben | |
DE69327780D1 (de) | Verfahren und Vorrichtung zum Gefrieren von Nahrungsmitteln | |
DE59605457D1 (de) | Verfahren und Einrichtung zum Austragen von flüssigem Lot | |
DE69319544D1 (de) | Verfahren und Vorrichtung zum stufenweisen Abbau von Videodaten | |
DE69528266D1 (de) | Verfahren und vorrichtung zum kontrollierten aufbringen von partikeln auf wafers | |
DE69327976D1 (de) | Verfahren und Vorrichtung zum Aufschmelzlöten | |
DE69322695D1 (de) | Verfahren und vorrichtung zum gefrieren | |
DE69313517D1 (de) | Ladungsträgerstrahlgerät und Verfahren zum Betrieb desselben | |
DE69210650D1 (de) | Vorrichtung und Verfahren zum Elektroplattieren | |
DE69427954D1 (de) | Verfahren und vorrichtung zum flüssigkeitsauftrag | |
DE69500725D1 (de) | Verfahren und Gerät zum Löten | |
DE59304970D1 (de) | Vorrichtung und Verfahren zum Einspritzen | |
DE69332817D1 (de) | Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und Multiplikator | |
DE69211728D1 (de) | Immunoassay-Element und Verfahren zum Immuntest | |
DE69205217D1 (de) | Vorrichtung und Verfahren zum Zusammenbau von Schaltungsstrukturen. | |
DE69024297D1 (de) | Verfahren und gerät zum mehrschichtigen auftragschweissen |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |
|
8339 | Ceased/non-payment of the annual fee |