DE69330870D1 - Planarisierungsverfahren von einer Halbleitervorrichtung - Google Patents

Planarisierungsverfahren von einer Halbleitervorrichtung

Info

Publication number
DE69330870D1
DE69330870D1 DE69330870T DE69330870T DE69330870D1 DE 69330870 D1 DE69330870 D1 DE 69330870D1 DE 69330870 T DE69330870 T DE 69330870T DE 69330870 T DE69330870 T DE 69330870T DE 69330870 D1 DE69330870 D1 DE 69330870D1
Authority
DE
Germany
Prior art keywords
semiconductor device
planarization method
planarization
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69330870T
Other languages
English (en)
Other versions
DE69330870T2 (de
Inventor
Shigeru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69330870D1 publication Critical patent/DE69330870D1/de
Publication of DE69330870T2 publication Critical patent/DE69330870T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
DE69330870T 1992-12-22 1993-12-22 Planarisierungsverfahren von einer Halbleitervorrichtung Expired - Fee Related DE69330870T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34261892 1992-12-22

Publications (2)

Publication Number Publication Date
DE69330870D1 true DE69330870D1 (de) 2001-11-08
DE69330870T2 DE69330870T2 (de) 2002-04-11

Family

ID=18355172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330870T Expired - Fee Related DE69330870T2 (de) 1992-12-22 1993-12-22 Planarisierungsverfahren von einer Halbleitervorrichtung

Country Status (4)

Country Link
US (1) US5540811A (de)
EP (1) EP0609551B1 (de)
KR (1) KR0133264B1 (de)
DE (1) DE69330870T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0977248A1 (de) * 1994-01-17 2000-02-02 Sony Corporation Verfahren zum Einebnen der Oberfläche einer Halbleiteranordnung
US5946591A (en) * 1994-11-07 1999-08-31 Texas Instruments Incorporated Method of making a semiconductor device having a flat surface
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures
US5683945A (en) * 1996-05-16 1997-11-04 Siemens Aktiengesellschaft Uniform trench fill recess by means of isotropic etching
KR100443020B1 (ko) * 1997-12-13 2004-09-18 삼성전자주식회사 표면 평탄화 기술을 이용한 반도체 소자 제조방법
US5928961A (en) * 1997-12-22 1999-07-27 Industrial Technology Research Institute Dishing inhibited shallow trench isolation
US6022788A (en) * 1997-12-23 2000-02-08 Stmicroelectronics, Inc. Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby
TW498440B (en) 1998-03-30 2002-08-11 Hitachi Ltd Manufacture method of semiconductor device
US6265315B1 (en) 1998-06-24 2001-07-24 Taiwan Semiconductor Manufacturing Company Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits
JP2000124305A (ja) * 1998-10-15 2000-04-28 Mitsubishi Electric Corp 半導体装置
US6287972B1 (en) 1999-03-04 2001-09-11 Philips Semiconductor, Inc. System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication
DE10053467A1 (de) * 2000-10-27 2002-05-16 Infineon Technologies Ag Verfahren zum Bilden von Kontakten in integrierten Schaltungen
US7390463B2 (en) * 2001-09-07 2008-06-24 Corning Incorporated Microcolumn-based, high-throughput microfluidic device
US6884729B2 (en) * 2002-02-11 2005-04-26 Cabot Microelectronics Corporation Global planarization method
KR101793160B1 (ko) * 2010-12-10 2017-11-03 삼성전자주식회사 반도체 소자 제조 방법
US8822287B2 (en) * 2010-12-10 2014-09-02 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices
KR101865566B1 (ko) * 2011-09-08 2018-06-11 삼성전자주식회사 수직형 메모리 장치의 제조 방법
JP2016207973A (ja) * 2015-04-28 2016-12-08 株式会社東芝 半導体装置の製造方法
KR102510707B1 (ko) 2016-07-12 2023-03-17 에스케이하이닉스 주식회사 전자 장치 및 그 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4662064A (en) * 1985-08-05 1987-05-05 Rca Corporation Method of forming multi-level metallization
US4836885A (en) * 1988-05-03 1989-06-06 International Business Machines Corporation Planarization process for wide trench isolation
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques

Also Published As

Publication number Publication date
EP0609551B1 (de) 2001-10-04
DE69330870T2 (de) 2002-04-11
KR940016580A (ko) 1994-07-23
EP0609551A1 (de) 1994-08-10
KR0133264B1 (ko) 1998-04-16
US5540811A (en) 1996-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee