DE69330739D1 - Digitale Mehrmaster-Übertragungstechnik mit einem eigenen Konkurrenzbus - Google Patents

Digitale Mehrmaster-Übertragungstechnik mit einem eigenen Konkurrenzbus

Info

Publication number
DE69330739D1
DE69330739D1 DE69330739T DE69330739T DE69330739D1 DE 69330739 D1 DE69330739 D1 DE 69330739D1 DE 69330739 T DE69330739 T DE 69330739T DE 69330739 T DE69330739 T DE 69330739T DE 69330739 D1 DE69330739 D1 DE 69330739D1
Authority
DE
Germany
Prior art keywords
competitor
bus
transmission technology
digital multi
master transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69330739T
Other languages
English (en)
Inventor
Robert M Bartis
Charles William Kevin Gritton
Ying T Tao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69330739D1 publication Critical patent/DE69330739D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
DE69330739T 1992-12-14 1993-12-01 Digitale Mehrmaster-Übertragungstechnik mit einem eigenen Konkurrenzbus Expired - Fee Related DE69330739D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/989,676 US5311512A (en) 1992-12-14 1992-12-14 Multiple-master digital communication technique utilizing a dedicated contention bus

Publications (1)

Publication Number Publication Date
DE69330739D1 true DE69330739D1 (de) 2001-10-18

Family

ID=25535352

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330739T Expired - Fee Related DE69330739D1 (de) 1992-12-14 1993-12-01 Digitale Mehrmaster-Übertragungstechnik mit einem eigenen Konkurrenzbus

Country Status (5)

Country Link
US (1) US5311512A (de)
EP (1) EP0602827B1 (de)
JP (1) JP2828887B2 (de)
CA (1) CA2106744C (de)
DE (1) DE69330739D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5642350A (en) * 1993-11-23 1997-06-24 Ericsson Inc. Peer to peer network for a mobile radio transceiver
JP3348330B2 (ja) * 1995-04-21 2002-11-20 ソニー株式会社 通信制御方法
US5740174A (en) * 1995-11-02 1998-04-14 Cypress Semiconductor Corp. Method and apparatus for performing collision detection and arbitration within an expansion bus having multiple transmission repeater units
AU751020B2 (en) * 1997-03-17 2002-08-08 Ge-Harris Railways Electronics, L.L.C. A communications system and method for interconnected networks having a linear topology, especially railways
US6385210B1 (en) 1998-04-17 2002-05-07 Ford Global Technologies, Inc. Method for detecting and resolving data corruption in a UART based communication network
US7865641B2 (en) * 2006-09-29 2011-01-04 Qimonda Ag Synchronization and scheduling of a dual master serial channel
US9481348B2 (en) * 2012-09-20 2016-11-01 Wabtec Holding Corp. System and method for addressing a pneumatic emergency in a helper locomotive

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063220A (en) * 1975-03-31 1977-12-13 Xerox Corporation Multipoint data communication system with collision detection
US4210780A (en) * 1978-03-27 1980-07-01 The Mitre Corporation Multiple access digital communications system
JPS5824061B2 (ja) * 1979-03-05 1983-05-19 横河電機株式会社 デ−タ通信制御方式
US4598285A (en) * 1983-05-27 1986-07-01 At&T Bell Laboratories Scheme for reducing transmission delay following collision of transmissions in communication networks
US4626843A (en) * 1983-09-27 1986-12-02 Trw Inc. Multi-master communication bus system with parallel bus request arbitration
US4654655A (en) * 1984-03-02 1987-03-31 Motorola, Inc. Multi-user serial data bus
US4635030A (en) * 1984-07-30 1987-01-06 Canadian Marconi Company Status display system
DE3480962D1 (de) * 1984-10-31 1990-02-08 Ibm Deutschland Verfahren und einrichtung zur steuerung einer sammelleitung.
JPS622742A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 衝突検出方式
US4740956A (en) * 1985-12-30 1988-04-26 Ibm Corporation Linear-space signalling for a circuit-switched network
JPH0646733B2 (ja) * 1987-06-30 1994-06-15 沖電気工業株式会社 １つの伝送媒体を共有する競合制御方式
US4852091A (en) * 1988-04-21 1989-07-25 Bell Communications Research, Inc. High capacity communication system utilizing OR-type channels
JPH06101736B2 (ja) * 1990-03-22 1994-12-12 株式会社ユニウエル 通信制御方法

Also Published As

Publication number Publication date
US5311512A (en) 1994-05-10
CA2106744C (en) 1999-02-16
JP2828887B2 (ja) 1998-11-25
EP0602827A3 (en) 1995-08-16
CA2106744A1 (en) 1994-06-15
JPH07154400A (ja) 1995-06-16
EP0602827B1 (de) 2001-09-12
EP0602827A2 (de) 1994-06-22

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee