DE69325767T2 - Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher - Google Patents

Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher

Info

Publication number
DE69325767T2
DE69325767T2 DE69325767T DE69325767T DE69325767T2 DE 69325767 T2 DE69325767 T2 DE 69325767T2 DE 69325767 T DE69325767 T DE 69325767T DE 69325767 T DE69325767 T DE 69325767T DE 69325767 T2 DE69325767 T2 DE 69325767T2
Authority
DE
Germany
Prior art keywords
eeprom
evaluating
dielectric layer
volatile eprom
eeprom memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325767T
Other languages
English (en)
Other versions
DE69325767D1 (de
Inventor
Paolo Giuseppe Cappelletti
Leonardo Ravazzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69325767D1 publication Critical patent/DE69325767D1/de
Publication of DE69325767T2 publication Critical patent/DE69325767T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
DE69325767T 1992-10-29 1993-04-01 Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher Expired - Fee Related DE69325767T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830589A EP0594920B1 (de) 1992-10-29 1992-10-29 Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher

Publications (2)

Publication Number Publication Date
DE69325767D1 DE69325767D1 (de) 1999-09-02
DE69325767T2 true DE69325767T2 (de) 1999-12-02

Family

ID=8212193

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69229673T Expired - Fee Related DE69229673T2 (de) 1992-10-29 1992-10-29 Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
DE69325767T Expired - Fee Related DE69325767T2 (de) 1992-10-29 1993-04-01 Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69229673T Expired - Fee Related DE69229673T2 (de) 1992-10-29 1992-10-29 Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher

Country Status (4)

Country Link
US (2) US5515318A (de)
EP (1) EP0594920B1 (de)
JP (1) JPH077140A (de)
DE (2) DE69229673T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10103060B4 (de) * 2000-01-26 2006-06-08 Infineon Technologies Ag Verfahren zum Testen einer ein Floating-Gate aufweisenden Speicherzelle und Anordnung zur Durchführung dieses Verfahrens

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EP0594920B1 (de) * 1992-10-29 1999-07-28 STMicroelectronics S.r.l. Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
EP0595775B1 (de) * 1992-10-29 1999-07-28 STMicroelectronics S.r.l. Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
US5682472A (en) * 1995-03-17 1997-10-28 Aehr Test Systems Method and system for testing memory programming devices
US5870407A (en) * 1996-05-24 1999-02-09 Advanced Micro Devices, Inc. Method of screening memory cells at room temperature that would be rejected during hot temperature programming tests
US6049213A (en) * 1998-01-27 2000-04-11 International Business Machines Corporation Method and system for testing the reliability of gate dielectric films
US6472233B1 (en) * 1999-08-02 2002-10-29 Advanced Micro Devices, Inc. MOSFET test structure for capacitance-voltage measurements
US6128219A (en) * 1999-10-27 2000-10-03 Stmicroelectronics, S.R.L. Nonvolatile memory test structure and nonvolatile memory reliability test method
KR100363842B1 (ko) * 1999-12-27 2002-12-06 주식회사 하이닉스반도체 플래쉬 메모리의 소오스 콘택 모니터링 방법
JP3848064B2 (ja) * 2000-08-07 2006-11-22 シャープ株式会社 半導体不揮発性メモリの試験方法
US6407953B1 (en) 2001-02-02 2002-06-18 Matrix Semiconductor, Inc. Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays
US7177181B1 (en) 2001-03-21 2007-02-13 Sandisk 3D Llc Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
TW520513B (en) * 2001-08-02 2003-02-11 Macronix Int Co Ltd Accelerated test method and circuit for non-volatile memory
US6684173B2 (en) 2001-10-09 2004-01-27 Micron Technology, Inc. System and method of testing non-volatile memory cells
US6768685B1 (en) 2001-11-16 2004-07-27 Mtrix Semiconductor, Inc. Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor
JP2005518630A (ja) * 2002-02-26 2005-06-23 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 不揮発性メモリテスト構造および方法
US6982901B1 (en) * 2003-01-31 2006-01-03 Hewlett-Packard Development Company, L.P. Memory device and method of use
US7160740B2 (en) 2003-07-07 2007-01-09 Advanced Micro Devices, Inc. Methods of controlling properties and characteristics of a gate insulation layer based upon electrical test data, and system for performing same
US7177183B2 (en) 2003-09-30 2007-02-13 Sandisk 3D Llc Multiple twin cell non-volatile memory array and logic block structure and method therefor
US6885214B1 (en) 2003-10-20 2005-04-26 Taiwan Semiconductor Manufacturing Company Method for measuring capacitance-voltage curves for transistors
JP2007157282A (ja) * 2005-12-07 2007-06-21 Elpida Memory Inc ウェハ・バーンイン・テスト方法、ウェハ・バーンイン・テスト装置及び半導体記憶装置
US7512509B2 (en) 2007-04-26 2009-03-31 International Business Machines Corporation M1 testable addressable array for device parameter characterization
KR101287447B1 (ko) * 2007-08-28 2013-07-19 삼성전자주식회사 이이피롬 셀, 이이피롬 셀 제조 방법 및 이이피롬 셀에서의데이터 읽기 방법

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US4243937A (en) * 1979-04-06 1981-01-06 General Instrument Corporation Microelectronic device and method for testing same
US4545112A (en) * 1983-08-15 1985-10-08 Alphasil Incorporated Method of manufacturing thin film transistors and transistors made thereby
US5155701A (en) * 1985-02-08 1992-10-13 Hitachi, Ltd. Semiconductor integrated circuit device and method of testing the same
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
US4967394A (en) * 1987-09-09 1990-10-30 Kabushiki Kaisha Toshiba Semiconductor memory device having a test cell array
US5247346A (en) * 1988-02-05 1993-09-21 Emanuel Hazani E2 PROM cell array including single charge emitting means per row
US4841482A (en) * 1988-02-17 1989-06-20 Intel Corporation Leakage verification for flash EPROM
US4829014A (en) * 1988-05-02 1989-05-09 General Electric Company Screenable power chip mosaics, a method for fabricating large power semiconductor chips
US4963825A (en) * 1989-12-21 1990-10-16 Intel Corporation Method of screening EPROM-related devices for endurance failure
JPH03283200A (ja) * 1990-03-30 1991-12-13 Toshiba Corp 不揮発性半導体記憶装置及びこれに用いられるメモリセルトランジスタのしきい値電圧の測定方法
JP2530243B2 (ja) * 1990-05-24 1996-09-04 株式会社シンク・ラボラトリー ユニット移動式現像方法及びユニット移動式現像装置
JP2635810B2 (ja) * 1990-09-28 1997-07-30 株式会社東芝 半導体記憶装置
US5243554A (en) * 1991-05-09 1993-09-07 Synaptics, Incorporated Writable analog reference voltage storage device
US5283454A (en) * 1992-09-11 1994-02-01 Motorola, Inc. Semiconductor device including very low sheet resistivity buried layer
EP0595775B1 (de) * 1992-10-29 1999-07-28 STMicroelectronics S.r.l. Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
EP0594920B1 (de) * 1992-10-29 1999-07-28 STMicroelectronics S.r.l. Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10103060B4 (de) * 2000-01-26 2006-06-08 Infineon Technologies Ag Verfahren zum Testen einer ein Floating-Gate aufweisenden Speicherzelle und Anordnung zur Durchführung dieses Verfahrens

Also Published As

Publication number Publication date
DE69229673D1 (de) 1999-09-02
DE69229673T2 (de) 1999-12-02
US5515318A (en) 1996-05-07
US5793675A (en) 1998-08-11
DE69325767D1 (de) 1999-09-02
EP0594920A1 (de) 1994-05-04
JPH077140A (ja) 1995-01-10
EP0594920B1 (de) 1999-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee