DE69230156D1 - Herstellungsverfahren für Kondensator mit gestapelter Flossenstruktur und mit reduzierter Flossendicke - Google Patents

Herstellungsverfahren für Kondensator mit gestapelter Flossenstruktur und mit reduzierter Flossendicke

Info

Publication number
DE69230156D1
DE69230156D1 DE69230156T DE69230156T DE69230156D1 DE 69230156 D1 DE69230156 D1 DE 69230156D1 DE 69230156 T DE69230156 T DE 69230156T DE 69230156 T DE69230156 T DE 69230156T DE 69230156 D1 DE69230156 D1 DE 69230156D1
Authority
DE
Germany
Prior art keywords
capacitor
manufacturing process
fin
reduced
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230156T
Other languages
English (en)
Other versions
DE69230156T2 (de
Inventor
Taiji Ema
Higashitani Masaaki
Toshimi Ikeda
Michiari Kawano
Hiroshi Nomura
Masaya Katayama
Masahiro Kuwamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3186155A external-priority patent/JP2827181B2/ja
Priority claimed from JP3239045A external-priority patent/JP3044861B2/ja
Priority claimed from JP4031754A external-priority patent/JPH05235292A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69230156D1 publication Critical patent/DE69230156D1/de
Publication of DE69230156T2 publication Critical patent/DE69230156T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69230156T 1991-07-25 1992-07-17 Herstellungsverfahren für Kondensator mit gestapelter Flossenstruktur und mit reduzierter Flossendicke Expired - Fee Related DE69230156T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3186155A JP2827181B2 (ja) 1991-07-25 1991-07-25 半導体装置及びその製造方法
JP3239045A JP3044861B2 (ja) 1991-09-19 1991-09-19 半導体記憶装置
JP4031754A JPH05235292A (ja) 1992-02-19 1992-02-19 フィン構造体の製造方法

Publications (2)

Publication Number Publication Date
DE69230156D1 true DE69230156D1 (de) 1999-11-18
DE69230156T2 DE69230156T2 (de) 2000-05-25

Family

ID=27287451

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230156T Expired - Fee Related DE69230156T2 (de) 1991-07-25 1992-07-17 Herstellungsverfahren für Kondensator mit gestapelter Flossenstruktur und mit reduzierter Flossendicke

Country Status (4)

Country Link
US (1) US5661340A (de)
EP (2) EP0782195B1 (de)
KR (1) KR960005243B1 (de)
DE (1) DE69230156T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525534A (en) * 1992-03-13 1996-06-11 Fujitsu Limited Method of producing a semiconductor device using a reticle having a polygonal shaped hole
JPH09129848A (ja) * 1995-11-06 1997-05-16 Mitsubishi Electric Corp キャパシタを有する半導体装置の製造方法
US5879988A (en) * 1996-06-12 1999-03-09 Mosel Vitelic Incorporated Capacitor of a DRAM cell and method of making same
KR100250174B1 (ko) * 1996-06-14 2000-04-01 흥 치우 후 Dram 셀의 커패시터의 제조 방법
JPH10144886A (ja) * 1996-09-11 1998-05-29 Toshiba Corp 半導体装置及びその製造方法
CN1063288C (zh) * 1997-05-23 2001-03-14 联华电子股份有限公司 与非逻辑非晶硅只读存储器及其制造方法
US6022782A (en) * 1997-05-30 2000-02-08 Stmicroelectronics, Inc. Method for forming integrated circuit transistors using sacrificial spacer
US5885867A (en) * 1997-12-03 1999-03-23 Samsung Electronics Co., Ltd. Methods of forming hemispherical grained silicon layers including anti-nucleation gases
KR100339244B1 (ko) 1999-06-30 2002-05-31 박종섭 고부하저항 타입의 에스램 제조방법
DE10016971A1 (de) * 2000-04-06 2001-10-11 Angew Solarenergie Ase Gmbh Verfahren und Vorrichtung zum Beschichten und/oder Behandeln eines Substrats
US6559017B1 (en) * 2002-06-13 2003-05-06 Advanced Micro Devices, Inc. Method of using amorphous carbon as spacer material in a disposable spacer process
JP4085891B2 (ja) * 2003-05-30 2008-05-14 ソニー株式会社 半導体装置およびその製造方法
US7102204B2 (en) * 2004-06-29 2006-09-05 International Business Machines Corporation Integrated SOI fingered decoupling capacitor
CN105845630B (zh) * 2015-01-13 2019-03-12 旺宏电子股份有限公司 一种存储器装置及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS634670A (ja) * 1986-06-25 1988-01-09 Hitachi Ltd 半導体集積回路装置の製造方法
EP0750347B1 (de) * 1987-06-17 2002-05-08 Fujitsu Limited Dynamisches Speicherbauteil mit wahlfreiem Zugriff und Verfahren zu seiner Herstellung
JPS6481227A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Etching method
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
JP2835723B2 (ja) * 1988-02-26 1998-12-14 富士通株式会社 キャパシタ及びキャパシタの製造方法
JPH0338061A (ja) * 1989-07-05 1991-02-19 Fujitsu Ltd 半導体記憶装置
US4994404A (en) * 1989-08-28 1991-02-19 Motorola, Inc. Method for forming a lightly-doped drain (LDD) structure in a semiconductor device
EP0764974B1 (de) * 1990-03-08 2006-06-14 Fujitsu Limited Schichtstruktur mit Kontaktöffnung und Verfahren zur Herstellung derselben
US5223729A (en) * 1990-09-26 1993-06-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device and a method of producing the same

Also Published As

Publication number Publication date
EP0528183A2 (de) 1993-02-24
KR960005243B1 (ko) 1996-04-23
US5661340A (en) 1997-08-26
EP0782195A3 (de) 1997-11-05
EP0528183B1 (de) 1997-10-08
DE69230156T2 (de) 2000-05-25
EP0782195A2 (de) 1997-07-02
EP0528183A3 (en) 1993-05-12
EP0782195B1 (de) 1999-10-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee