DE69229081D1 - Mikroprozessor mit externem Speicher - Google Patents

Mikroprozessor mit externem Speicher

Info

Publication number
DE69229081D1
DE69229081D1 DE69229081T DE69229081T DE69229081D1 DE 69229081 D1 DE69229081 D1 DE 69229081D1 DE 69229081 T DE69229081 T DE 69229081T DE 69229081 T DE69229081 T DE 69229081T DE 69229081 D1 DE69229081 D1 DE 69229081D1
Authority
DE
Germany
Prior art keywords
input
output
control
level
external bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69229081T
Other languages
English (en)
Other versions
DE69229081T2 (de
Inventor
William M Johnson
David B Witt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69229081D1 publication Critical patent/DE69229081D1/de
Application granted granted Critical
Publication of DE69229081T2 publication Critical patent/DE69229081T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69229081T 1991-03-01 1992-01-06 Mikroprozessor mit externem Speicher Expired - Lifetime DE69229081T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66331491A 1991-03-01 1991-03-01

Publications (2)

Publication Number Publication Date
DE69229081D1 true DE69229081D1 (de) 1999-06-10
DE69229081T2 DE69229081T2 (de) 2000-01-05

Family

ID=24661291

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69233510T Expired - Lifetime DE69233510T2 (de) 1991-03-01 1992-01-06 Ausgangspuffer für Mikroprozessor
DE69229081T Expired - Lifetime DE69229081T2 (de) 1991-03-01 1992-01-06 Mikroprozessor mit externem Speicher

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69233510T Expired - Lifetime DE69233510T2 (de) 1991-03-01 1992-01-06 Ausgangspuffer für Mikroprozessor

Country Status (5)

Country Link
US (2) US5805912A (de)
EP (2) EP0913777B1 (de)
JP (3) JPH04319753A (de)
AT (2) ATE179810T1 (de)
DE (2) DE69233510T2 (de)

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JPH07210445A (ja) * 1994-01-20 1995-08-11 Mitsubishi Electric Corp 半導体記憶装置およびコンピュータ
JP3490131B2 (ja) * 1994-01-21 2004-01-26 株式会社ルネサステクノロジ データ転送制御方法、データプロセッサ及びデータ処理システム
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
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US5742840A (en) 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
JP3643425B2 (ja) * 1996-02-29 2005-04-27 富士通株式会社 データ処理方法、データ処理装置及びインターフェイスコントローラ
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US6209072B1 (en) * 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
US6289502B1 (en) * 1997-09-26 2001-09-11 Massachusetts Institute Of Technology Model-based software design and validation
US6550013B1 (en) * 1999-09-02 2003-04-15 International Business Machines Corporation Memory clock generator and method therefor
US6704820B1 (en) * 2000-02-18 2004-03-09 Hewlett-Packard Development Company, L.P. Unified cache port consolidation
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US6909659B2 (en) * 2001-08-30 2005-06-21 Micron Technology, Inc. Zero power chip standby mode
US7171499B2 (en) * 2003-10-10 2007-01-30 Advanced Micro Devices, Inc. Processor surrogate for use in multiprocessor systems and multiprocessor system using same
US7676839B2 (en) * 2004-03-15 2010-03-09 Xceedid Systems and methods for access control
US7900253B2 (en) * 2005-03-08 2011-03-01 Xceedid Corporation Systems and methods for authorization credential emulation
JP4692231B2 (ja) * 2005-11-04 2011-06-01 株式会社デンソー 車両用の電子制御装置
US7636803B2 (en) * 2006-09-28 2009-12-22 Advanced Micro Devices, Inc. Device and method for transferring data between devices
US7681099B2 (en) * 2007-05-17 2010-03-16 Advanced Micro Devices, Inc. Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test
US7737752B2 (en) * 2007-05-17 2010-06-15 Globalfoundries Inc Techniques for integrated circuit clock management
US8014485B2 (en) * 2007-05-17 2011-09-06 Advanced Micro Devices, Inc. Techniques for integrated circuit clock management using multiple clock generators
US7921318B2 (en) * 2007-05-17 2011-04-05 Globalfoundries Inc. Techniques for integrated circuit clock management using pulse skipping
US8015428B2 (en) * 2007-06-12 2011-09-06 Renesas Electronics Corporation Processing device and clock control method
US8575972B2 (en) * 2009-03-23 2013-11-05 Advanced Micro Devices, Inc. Digital frequency synthesizer device and method thereof
US9240229B1 (en) 2012-03-15 2016-01-19 Gsi Technology, Inc. Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US10521229B2 (en) 2016-12-06 2019-12-31 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10249362B2 (en) 2016-12-06 2019-04-02 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features

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JPS5266346A (en) * 1975-11-29 1977-06-01 Tokyo Electric Co Ltd Synch. clock control of microcomputer system
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US5179667A (en) * 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
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US5263172A (en) * 1990-04-16 1993-11-16 International Business Machines Corporation Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
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Also Published As

Publication number Publication date
JP3811764B2 (ja) 2006-08-23
EP0913777B1 (de) 2005-05-11
EP0913777A2 (de) 1999-05-06
DE69233510T2 (de) 2006-02-02
DE69233510D1 (de) 2005-06-16
ATE295571T1 (de) 2005-05-15
EP0507427B1 (de) 1999-05-06
JPH04319753A (ja) 1992-11-10
DE69229081T2 (de) 2000-01-05
EP0507427A1 (de) 1992-10-07
JP4008948B2 (ja) 2007-11-14
ATE179810T1 (de) 1999-05-15
JP2006228239A (ja) 2006-08-31
US5805912A (en) 1998-09-08
EP0913777A3 (de) 2003-11-19
US5828869A (en) 1998-10-27
JP2005216268A (ja) 2005-08-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition