DE69228784D1 - Fehlereinkapselungs-System und Verfahren für Mehrrechner mit geteiltem Speicher - Google Patents

Fehlereinkapselungs-System und Verfahren für Mehrrechner mit geteiltem Speicher

Info

Publication number
DE69228784D1
DE69228784D1 DE69228784T DE69228784T DE69228784D1 DE 69228784 D1 DE69228784 D1 DE 69228784D1 DE 69228784 T DE69228784 T DE 69228784T DE 69228784 T DE69228784 T DE 69228784T DE 69228784 D1 DE69228784 D1 DE 69228784D1
Authority
DE
Germany
Prior art keywords
fault
datum
signal
detected
response packet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69228784T
Other languages
English (en)
Other versions
DE69228784T2 (de
Inventor
Steven J Frank
William F Mann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69228784D1 publication Critical patent/DE69228784D1/de
Publication of DE69228784T2 publication Critical patent/DE69228784T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
DE69228784T 1991-09-23 1992-09-16 Fehlereinkapselungs-System und Verfahren für Mehrrechner mit geteiltem Speicher Expired - Fee Related DE69228784T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76367791A 1991-09-23 1991-09-23

Publications (2)

Publication Number Publication Date
DE69228784D1 true DE69228784D1 (de) 1999-05-06
DE69228784T2 DE69228784T2 (de) 1999-12-23

Family

ID=25068502

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69228784T Expired - Fee Related DE69228784T2 (de) 1991-09-23 1992-09-16 Fehlereinkapselungs-System und Verfahren für Mehrrechner mit geteiltem Speicher

Country Status (5)

Country Link
EP (1) EP0534665B1 (de)
JP (1) JPH05298190A (de)
AT (1) ATE178417T1 (de)
CA (1) CA2078311A1 (de)
DE (1) DE69228784T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001134546A (ja) * 1999-11-05 2001-05-18 Nec Corp マルチプロセッサシステムの障害処理方法
JP5800058B2 (ja) * 2014-05-26 2015-10-28 富士通株式会社 情報処理装置、制御方法および制御プログラム

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503535A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for recovery from failures in a multiprocessing system
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
CA2019300C (en) * 1989-06-22 2001-06-12 Kendall Square Research Corporation Multiprocessor system with shared memory

Also Published As

Publication number Publication date
DE69228784T2 (de) 1999-12-23
EP0534665B1 (de) 1999-03-31
CA2078311A1 (en) 1993-03-24
EP0534665A3 (en) 1993-07-28
EP0534665A2 (de) 1993-03-31
JPH05298190A (ja) 1993-11-12
ATE178417T1 (de) 1999-04-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee