DE69228204D1 - Gerät zur Ausführung von Multiplikationen mit verringertem Energieverbrauch und Verfahren dazu - Google Patents

Gerät zur Ausführung von Multiplikationen mit verringertem Energieverbrauch und Verfahren dazu

Info

Publication number
DE69228204D1
DE69228204D1 DE69228204T DE69228204T DE69228204D1 DE 69228204 D1 DE69228204 D1 DE 69228204D1 DE 69228204 T DE69228204 T DE 69228204T DE 69228204 T DE69228204 T DE 69228204T DE 69228204 D1 DE69228204 D1 DE 69228204D1
Authority
DE
Germany
Prior art keywords
energy consumption
method therefor
reduced energy
performing multiplications
multiplications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69228204T
Other languages
English (en)
Inventor
James W Girardeau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69228204D1 publication Critical patent/DE69228204D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)
DE69228204T 1991-05-06 1992-04-30 Gerät zur Ausführung von Multiplikationen mit verringertem Energieverbrauch und Verfahren dazu Expired - Lifetime DE69228204D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/696,407 US5128890A (en) 1991-05-06 1991-05-06 Apparatus for performing multiplications with reduced power and a method therefor

Publications (1)

Publication Number Publication Date
DE69228204D1 true DE69228204D1 (de) 1999-03-04

Family

ID=24796941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69228204T Expired - Lifetime DE69228204D1 (de) 1991-05-06 1992-04-30 Gerät zur Ausführung von Multiplikationen mit verringertem Energieverbrauch und Verfahren dazu

Country Status (4)

Country Link
US (2) US5128890A (de)
EP (1) EP0513595B1 (de)
JP (1) JP3177922B2 (de)
DE (1) DE69228204D1 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL99660A0 (en) * 1991-10-07 1992-08-18 Ibm Israel Random number generator
US5420815A (en) * 1991-10-29 1995-05-30 Advanced Micro Devices, Inc. Digital multiplication and accumulation system
US5200912A (en) * 1991-11-19 1993-04-06 Advanced Micro Devices, Inc. Apparatus for providing power to selected portions of a multiplying device
JP2862723B2 (ja) * 1992-03-16 1999-03-03 沖電気工業株式会社 ディジタル信号処理装置
JP3050255B2 (ja) * 1992-10-14 2000-06-12 富士通株式会社 Ｅｃｌ−ｃｍｏｓレベル変換回路
US5422805A (en) * 1992-10-21 1995-06-06 Motorola, Inc. Method and apparatus for multiplying two numbers using signed arithmetic
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
DE4242929A1 (de) * 1992-12-18 1994-06-23 Philips Patentverwaltung Schaltungsanordnung zum Bilden der Summe von Produkten
US5650952A (en) * 1992-12-18 1997-07-22 U.S. Philips Corporation Circuit arrangement for forming the sum of products
US5471663A (en) * 1993-07-01 1995-11-28 Motorola, Inc. Expanded microcomputer system for controlling radio frequency interference
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US5465409A (en) * 1994-03-07 1995-11-07 Motorola, Inc. Radio architecture with dual frequency source selection
US5442576A (en) * 1994-05-26 1995-08-15 Motorola, Inc. Multibit shifting apparatus, data processor using same, and method therefor
US5489862A (en) * 1994-11-18 1996-02-06 Texas Instruments Incorporated Output driver with slew and skew rate control
US5787029A (en) * 1994-12-19 1998-07-28 Crystal Semiconductor Corp. Ultra low power multiplier
US5600674A (en) * 1995-03-02 1997-02-04 Motorola Inc. Method and apparatus of an enhanced digital signal processor
US5784602A (en) * 1996-10-08 1998-07-21 Advanced Risc Machines Limited Method and apparatus for digital signal processing for integrated circuit architecture
JPH10187416A (ja) * 1996-12-20 1998-07-21 Nec Corp 浮動小数点演算装置
US5969554A (en) * 1997-06-09 1999-10-19 International Business Machines Corp. Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting
US6604120B1 (en) * 1997-09-04 2003-08-05 Cirrus Logic, Inc. Multiplier power saving design
US6404228B1 (en) * 1998-01-09 2002-06-11 Ralph T. Luna Apparatus for translating digital signals
US6760380B1 (en) 1998-12-07 2004-07-06 Lynk Labs, Inc. Data transmission apparatus and method
JP3598008B2 (ja) * 1998-12-25 2004-12-08 富士通株式会社 半導体装置
US6317840B1 (en) 1999-03-24 2001-11-13 International Business Machines Corporation Control of multiple equivalent functional units for power reduction
US6750694B1 (en) * 2000-11-28 2004-06-15 Texas Instruments Incorporated Signal clipping circuit
ITTO20010531A1 (it) * 2001-06-01 2002-12-01 St Microelectronics Srl Buffer di uscita per una memoria non volatile con controllo dello slew rate ottimizzato.
KR100490623B1 (ko) * 2003-02-24 2005-05-17 삼성에스디아이 주식회사 버퍼 회로 및 이를 이용한 액티브 매트릭스 표시 장치
US7290121B2 (en) * 2003-06-12 2007-10-30 Advanced Micro Devices, Inc. Method and data processor with reduced stalling due to operand dependencies
US7424501B2 (en) 2003-06-30 2008-09-09 Intel Corporation Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations
US7539714B2 (en) * 2003-06-30 2009-05-26 Intel Corporation Method, apparatus, and instruction for performing a sign operation that multiplies
US7330389B1 (en) * 2005-02-03 2008-02-12 Cypress Semiconductor Corp. Address detection system and method that compensates for process, temperature, and/or voltage fluctuations
US8015229B2 (en) * 2005-06-01 2011-09-06 Atmel Corporation Apparatus and method for performing efficient multiply-accumulate operations in microprocessors
US7711765B2 (en) 2006-02-17 2010-05-04 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus to perform multiply-and-accumulate operations
TWI407694B (zh) * 2010-01-27 2013-09-01 Novatek Microelectronics Corp 可抑制電壓過衝之輸出緩衝電路及方法
JP2011186512A (ja) * 2010-03-04 2011-09-22 Nec Corp コンパイラ装置、及びコンパイル方法
US9152382B2 (en) * 2012-10-31 2015-10-06 Intel Corporation Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values
JP6484957B2 (ja) * 2014-08-25 2019-03-20 サンケン電気株式会社 演算処理装置
US9473163B1 (en) * 2015-07-29 2016-10-18 Mediatek Inc. Preamplifier circuit and SAR ADC using the same
US10372416B2 (en) * 2017-04-28 2019-08-06 Intel Corporation Multiply-accumulate “0” data gating
US10318317B2 (en) * 2017-05-12 2019-06-11 Tenstorrent Inc. Processing core with operation suppression based on contribution estimate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701874A (en) * 1983-04-06 1987-10-20 Nec Corporation Digital signal processing apparatus
US4683547A (en) * 1984-10-25 1987-07-28 International Business Machines Corporation Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance
JPS62256129A (ja) * 1986-04-30 1987-11-07 Sony Corp 演算処理装置
FR2604270B1 (fr) * 1986-09-22 1991-10-18 Jutand Francis Additionneur binaire comportant un operande fixe, et multiplieur binaire parallele-serie comprenant un tel additionneur
JPH0786824B2 (ja) * 1988-08-12 1995-09-20 日本電気株式会社 部分積生成回路
NL8901170A (nl) * 1989-05-10 1990-12-03 Philips Nv Geintegreerde schakeling met een signaalniveauconverter.
US5038057A (en) * 1990-05-29 1991-08-06 Motorola, Inc. ECL to CMOS logic translator

Also Published As

Publication number Publication date
US5128890A (en) 1992-07-07
EP0513595A2 (de) 1992-11-19
EP0513595A3 (en) 1993-05-26
JPH05143324A (ja) 1993-06-11
JP3177922B2 (ja) 2001-06-18
EP0513595B1 (de) 1999-01-20
US5293081A (en) 1994-03-08

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Legal Events

Date Code Title Description
8332 No legal effect for de