DE69232045D1 - Vorrichtung und verfahren zur ausführung von instruktionen in nicht sequentieller reihenfolge - Google Patents

Vorrichtung und verfahren zur ausführung von instruktionen in nicht sequentieller reihenfolge

Info

Publication number
DE69232045D1
DE69232045D1 DE69232045T DE69232045T DE69232045D1 DE 69232045 D1 DE69232045 D1 DE 69232045D1 DE 69232045 T DE69232045 T DE 69232045T DE 69232045 T DE69232045 T DE 69232045T DE 69232045 D1 DE69232045 D1 DE 69232045D1
Authority
DE
Germany
Prior art keywords
sequential order
implementing instructions
implementing
instructions
sequential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69232045T
Other languages
English (en)
Other versions
DE69232045T2 (de
Inventor
R Church
S Schibinger
T Jennings
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of DE69232045D1 publication Critical patent/DE69232045D1/de
Application granted granted Critical
Publication of DE69232045T2 publication Critical patent/DE69232045T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Retry When Errors Occur (AREA)
  • Multi Processors (AREA)
DE69232045T 1991-11-04 1992-11-03 Vorrichtung und verfahren zur ausführung von instruktionen in nicht sequentieller reihenfolge Expired - Fee Related DE69232045T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/787,676 US5280615A (en) 1990-03-23 1991-11-04 Out of order job processing method and apparatus
PCT/US1992/009418 WO1993009492A2 (en) 1991-11-04 1992-11-03 Out of order job processing method and apparatus

Publications (2)

Publication Number Publication Date
DE69232045D1 true DE69232045D1 (de) 2001-10-11
DE69232045T2 DE69232045T2 (de) 2002-06-06

Family

ID=25142243

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232045T Expired - Fee Related DE69232045T2 (de) 1991-11-04 1992-11-03 Vorrichtung und verfahren zur ausführung von instruktionen in nicht sequentieller reihenfolge

Country Status (6)

Country Link
US (1) US5280615A (de)
EP (1) EP0565705B1 (de)
JP (1) JP3335352B2 (de)
KR (1) KR100280161B1 (de)
DE (1) DE69232045T2 (de)
WO (1) WO1993009492A2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506974A (en) * 1990-03-23 1996-04-09 Unisys Corporation Method and means for concatenating multiple instructions
US5404557A (en) * 1991-11-22 1995-04-04 Matsushita Electric Industrial Co., Ltd. Data processor with plural instruction execution parts for synchronized parallel processing and exception handling
US5481683A (en) * 1992-10-30 1996-01-02 International Business Machines Corporation Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
US5748937A (en) * 1993-08-26 1998-05-05 Intel Corporation Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions
US5724536A (en) * 1994-01-04 1998-03-03 Intel Corporation Method and apparatus for blocking execution of and storing load operations during their execution
US5694553A (en) * 1994-01-04 1997-12-02 Intel Corporation Method and apparatus for determining the dispatch readiness of buffered load operations in a processor
US6047369A (en) * 1994-02-28 2000-04-04 Intel Corporation Flag renaming and flag masks within register alias table
GB2287111B (en) * 1994-03-01 1998-08-05 Intel Corp Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
US5625788A (en) * 1994-03-01 1997-04-29 Intel Corporation Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto
JP3308704B2 (ja) 1994-04-20 2002-07-29 キヤノン株式会社 画像形成装置、および画像形成装置の制御方法
US5666506A (en) * 1994-10-24 1997-09-09 International Business Machines Corporation Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
WO1997015001A2 (en) * 1995-10-06 1997-04-24 Patriot Scientific Corporation Risc microprocessor architecture
US5758117A (en) * 1995-12-14 1998-05-26 International Business Machines Corporation Method and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processor
US5781790A (en) * 1995-12-29 1998-07-14 Intel Corporation Method and apparatus for performing floating point to integer transfers and vice versa
US5784639A (en) * 1995-12-29 1998-07-21 Intel Corporation Load buffer integrated dynamic decoding logic
US5838942A (en) * 1996-03-01 1998-11-17 Hewlett-Packard Company Panic trap system and method
GB2348720B (en) * 1996-03-01 2000-11-22 Hewlett Packard Co Panic trap system and method
US5745780A (en) * 1996-03-27 1998-04-28 International Business Machines Corporation Method and apparatus for source lookup within a central processing unit
JP2000076353A (ja) 1998-09-03 2000-03-14 Toshiba Corp 業務指示シートによる業務処理システム
US6029174A (en) * 1998-10-31 2000-02-22 M/A/R/C Inc. Apparatus and system for an adaptive data management architecture
US6185555B1 (en) 1998-10-31 2001-02-06 M/A/R/C Inc. Method and apparatus for data management using an event transition network
US6615375B1 (en) * 2000-02-03 2003-09-02 International Business Machines Corporation Method and apparatus for tolerating unrecoverable errors in a multi-processor data processing system
JP4194532B2 (ja) * 2004-06-16 2008-12-10 キヤノン株式会社 情報処理装置及びジョブ転送制御方法
US7751079B2 (en) * 2004-08-11 2010-07-06 Xerox Corporation Method and system for managing print job files for a shared printer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4456958A (en) * 1982-06-08 1984-06-26 Burroughs Corporation System and method of renaming data items for dependency free code
US4468736A (en) * 1982-06-08 1984-08-28 Burroughs Corporation Mechanism for creating dependency free code for multiple processing elements
US4466061A (en) * 1982-06-08 1984-08-14 Burroughs Corporation Concurrent processing elements for using dependency free code
US4562538A (en) * 1983-05-16 1985-12-31 At&T Bell Laboratories Microprocessor having decision pointer to process restore position
US4720779A (en) * 1984-06-28 1988-01-19 Burroughs Corporation Stored logic program scanner for a data processor having internal plural data and instruction streams
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
US4773041A (en) * 1986-06-02 1988-09-20 Unisys Corporation System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor
US4825360A (en) * 1986-07-30 1989-04-25 Symbolics, Inc. System and method for parallel processing with mostly functional languages
SE454920B (sv) * 1986-10-03 1988-06-06 Ellemtel Utvecklings Ab Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instruktionssekvenser medelst separatminnen
US4980824A (en) * 1986-10-29 1990-12-25 United Technologies Corporation Event driven executive
US4875160A (en) * 1988-07-20 1989-10-17 Digital Equipment Corporation Method for implementing synchronous pipeline exception recovery
US5075844A (en) * 1989-05-24 1991-12-24 Tandem Computers Incorporated Paired instruction processor precise exception handling mechanism

Also Published As

Publication number Publication date
EP0565705A1 (de) 1993-10-20
KR930703642A (ko) 1993-11-30
KR100280161B1 (ko) 2001-02-01
JPH06504640A (ja) 1994-05-26
WO1993009492A2 (en) 1993-05-13
DE69232045T2 (de) 2002-06-06
EP0565705B1 (de) 2001-09-05
JP3335352B2 (ja) 2002-10-15
WO1993009492A3 (en) 1993-07-08
US5280615A (en) 1994-01-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee