DE69227294D1 - Programmierbare logische Vorrichtung - Google Patents
Programmierbare logische VorrichtungInfo
- Publication number
- DE69227294D1 DE69227294D1 DE69227294T DE69227294T DE69227294D1 DE 69227294 D1 DE69227294 D1 DE 69227294D1 DE 69227294 T DE69227294 T DE 69227294T DE 69227294 T DE69227294 T DE 69227294T DE 69227294 D1 DE69227294 D1 DE 69227294D1
- Authority
- DE
- Germany
- Prior art keywords
- logic
- programmable
- macrocells
- array
- product term
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/779,547 US5151623A (en) | 1985-03-29 | 1991-10-18 | Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69227294D1 true DE69227294D1 (de) | 1998-11-19 |
Family
ID=25116801
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69227294T Expired - Lifetime DE69227294D1 (de) | 1991-10-18 | 1992-08-10 | Programmierbare logische Vorrichtung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5151623A (de) |
EP (1) | EP0537885B1 (de) |
JP (1) | JPH05218199A (de) |
KR (1) | KR930009253A (de) |
AT (1) | ATE172336T1 (de) |
DE (1) | DE69227294D1 (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5477165A (en) * | 1986-09-19 | 1995-12-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5489857A (en) * | 1992-08-03 | 1996-02-06 | Advanced Micro Devices, Inc. | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
US5457409A (en) * | 1992-08-03 | 1995-10-10 | Advanced Micro Devices, Inc. | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
US5198705A (en) * | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5978831A (en) * | 1991-03-07 | 1999-11-02 | Lucent Technologies Inc. | Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates |
US5231312A (en) * | 1992-03-12 | 1993-07-27 | Atmel Corporation | Integrated logic circuit with functionally flexible input/output macrocells |
US5254886A (en) * | 1992-06-19 | 1993-10-19 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
US5463328A (en) * | 1993-03-08 | 1995-10-31 | Altera Corporation | Expanded programmable logic architecture |
US5625301A (en) * | 1995-05-18 | 1997-04-29 | Actel Corporation | Flexible FPGA input/output architecture |
US5781030A (en) * | 1995-06-02 | 1998-07-14 | Advanced Micro Devices, Inc. | Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD |
US5521529A (en) * | 1995-06-02 | 1996-05-28 | Advanced Micro Devices, Inc. | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation |
US5818254A (en) * | 1995-06-02 | 1998-10-06 | Advanced Micro Devices, Inc. | Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices |
US5589782A (en) * | 1995-06-02 | 1996-12-31 | Advanced Micro Devices, Inc. | Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions |
US6531890B1 (en) | 1995-06-02 | 2003-03-11 | Lattice Semiconductor Corporation | Programmable optimized-distribution logic allocator for a high-density complex PLD |
US6028446A (en) * | 1995-06-06 | 2000-02-22 | Advanced Micro Devices, Inc. | Flexible synchronous and asynchronous circuits for a very high density programmable logic device |
US5744980A (en) * | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US5936426A (en) | 1997-02-03 | 1999-08-10 | Actel Corporation | Logic function module for field programmable array |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6317804B1 (en) | 1998-11-30 | 2001-11-13 | Philips Semiconductors Inc. | Concurrent serial interconnect for integrating functional blocks in an integrated circuit device |
US6166564A (en) * | 1999-07-09 | 2000-12-26 | Intel Corporation | Control circuit for clock enable staging |
JP2002368727A (ja) * | 2001-06-04 | 2002-12-20 | Nec Corp | 半導体集積回路 |
US6874136B2 (en) * | 2002-01-10 | 2005-03-29 | M2000 | Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits |
US7111273B1 (en) * | 2003-07-03 | 2006-09-19 | Xilinx, Inc. | Softpal implementation and mapping technology for FPGAs with dedicated resources |
US8014480B1 (en) | 2007-03-09 | 2011-09-06 | Altera Corporation | Zero-delay serial communications circuitry for serial interconnects |
US9231865B2 (en) * | 2012-08-10 | 2016-01-05 | Wisconsin Alumni Research Foundation | Lookup engine with reconfigurable low latency computational tiles |
JP6225674B2 (ja) | 2013-12-02 | 2017-11-08 | 株式会社ソシオネクスト | 半導体装置および通信インタフェース回路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027315A (en) * | 1984-09-28 | 1991-06-25 | Advanced Micro Devices, Inc. | Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US5015884A (en) * | 1985-03-29 | 1991-05-14 | Advanced Micro Devices, Inc. | Multiple array high performance programmable logic device family |
US4758746A (en) * | 1985-08-12 | 1988-07-19 | Monolithic Memories, Inc. | Programmable logic array with added array of gates and added output routing flexibility |
US4772811A (en) * | 1986-07-04 | 1988-09-20 | Ricoh Company, Ltd. | Programmable logic device |
US5046035A (en) * | 1987-08-26 | 1991-09-03 | Ict International Cmos Tech., Inc. | High-performance user programmable logic device (PLD) |
US4878200A (en) * | 1987-12-30 | 1989-10-31 | Intel Corporation | Product term sharing/allocation in an EPROM array |
US4912342A (en) * | 1988-05-05 | 1990-03-27 | Altera Corporation | Programmable logic device with array blocks with programmable clocking |
US4871930A (en) * | 1988-05-05 | 1989-10-03 | Altera Corporation | Programmable logic device with array blocks connected via programmable interconnect |
US4879481A (en) * | 1988-09-02 | 1989-11-07 | Cypress Semiconductor Corporation | Dual I/O macrocell for high speed synchronous state machine |
US4894563A (en) * | 1988-10-11 | 1990-01-16 | Atmel Corporation | Output macrocell for programmable logic device |
US5079451A (en) * | 1990-12-13 | 1992-01-07 | Atmel Corporation | Programmable logic device with global and local product terms |
-
1991
- 1991-10-18 US US07/779,547 patent/US5151623A/en not_active Expired - Lifetime
-
1992
- 1992-08-10 EP EP92307282A patent/EP0537885B1/de not_active Expired - Lifetime
- 1992-08-10 DE DE69227294T patent/DE69227294D1/de not_active Expired - Lifetime
- 1992-08-10 AT AT92307282T patent/ATE172336T1/de not_active IP Right Cessation
- 1992-09-15 KR KR1019920016755A patent/KR930009253A/ko active IP Right Grant
- 1992-10-13 JP JP4301806A patent/JPH05218199A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0537885B1 (de) | 1998-10-14 |
KR930009253A (ko) | 1993-05-22 |
JPH05218199A (ja) | 1993-08-27 |
EP0537885A1 (de) | 1993-04-21 |
US5151623A (en) | 1992-09-29 |
ATE172336T1 (de) | 1998-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |