DE69029363D1 - Ausgangsschaltung für eine sourcengekoppelte FET-Logik - Google Patents

Ausgangsschaltung für eine sourcengekoppelte FET-Logik

Info

Publication number
DE69029363D1
DE69029363D1 DE69029363T DE69029363T DE69029363D1 DE 69029363 D1 DE69029363 D1 DE 69029363D1 DE 69029363 T DE69029363 T DE 69029363T DE 69029363 T DE69029363 T DE 69029363T DE 69029363 D1 DE69029363 D1 DE 69029363D1
Authority
DE
Germany
Prior art keywords
source
output circuit
fet logic
coupled fet
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029363T
Other languages
English (en)
Other versions
DE69029363T2 (de
Inventor
Hironori Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69029363D1 publication Critical patent/DE69029363D1/de
Application granted granted Critical
Publication of DE69029363T2 publication Critical patent/DE69029363T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
    • H03K19/09436—Source coupled field-effect logic [SCFL]

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE69029363T 1989-10-06 1990-10-05 Ausgangsschaltung für eine sourcengekoppelte FET-Logik Expired - Fee Related DE69029363T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1261574A JP2547863B2 (ja) 1989-10-06 1989-10-06 ソースカップルドｆｅｔロジック形出力回路

Publications (2)

Publication Number Publication Date
DE69029363D1 true DE69029363D1 (de) 1997-01-23
DE69029363T2 DE69029363T2 (de) 1997-04-30

Family

ID=17363808

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029363T Expired - Fee Related DE69029363T2 (de) 1989-10-06 1990-10-05 Ausgangsschaltung für eine sourcengekoppelte FET-Logik

Country Status (5)

Country Link
US (1) US5083046A (de)
EP (1) EP0425838B1 (de)
JP (1) JP2547863B2 (de)
KR (1) KR910008961A (de)
DE (1) DE69029363T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04278719A (ja) * 1991-03-06 1992-10-05 Toshiba Corp ソース電極結合形論理回路
US5869985A (en) * 1997-02-07 1999-02-09 Eic Enterprises Corporation Low voltage input buffer
US5942921A (en) * 1997-12-19 1999-08-24 Advanced Micro Devices, Inc. Differential comparator with an extended input range
KR100687625B1 (ko) * 2005-05-17 2007-02-27 박선근 신발끈 없는 신발
US9276529B1 (en) * 2014-10-03 2016-03-01 Hrl Laboratories, Llc High performance GaN operational amplifier with wide bandwidth and high dynamic range
US9673849B1 (en) 2016-08-16 2017-06-06 Advanced Micro Devices, Inc. Common mode extraction and tracking for data signaling

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1373639A (fr) * 1963-11-13 1964-09-25 Ass Elect Ind Perfectionnements aux circuits amplificateurs
US4093925A (en) * 1975-01-27 1978-06-06 Nippon Gakki Seizo Kabushiki Kaisha Method and system of driving power field effect transistor
JPS6264121A (ja) * 1985-09-13 1987-03-23 Toshiba Corp 電界効果トランジスタ回路
JPS62172819A (ja) * 1986-01-27 1987-07-29 Nec Corp 位相同期回路
JPS6374215A (ja) * 1986-09-17 1988-04-04 Mitsubishi Electric Corp 論理回路
JPS6474823A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Emitter follower circuit
US4857861A (en) * 1987-09-23 1989-08-15 U. S. Philips Corporation Amplifier arrangement with improved quiescent current control
US4945258A (en) * 1988-12-08 1990-07-31 Grumman Aerospace Corporation Monolithic gaAs high speed switch driver
JPH0777346B2 (ja) * 1988-12-28 1995-08-16 株式会社東芝 論理レベル変換回路

Also Published As

Publication number Publication date
JP2547863B2 (ja) 1996-10-23
EP0425838A1 (de) 1991-05-08
JPH03123221A (ja) 1991-05-27
KR910008961A (ko) 1991-05-31
DE69029363T2 (de) 1997-04-30
US5083046A (en) 1992-01-21
EP0425838B1 (de) 1996-12-11

Similar Documents

Publication Publication Date Title
DE68917235D1 (de) Programmierbare logische Schaltung.
DE3872184D1 (de) Logikanalysator.
DE68922240D1 (de) Komplementärausgangsschaltung für eine logische Schaltung.
DE68928959D1 (de) Logik-Schaltungsanordnungen
DE69021683D1 (de) Selbstprüfbare Randlogikschaltung.
NO901886L (no) Vekselretter-utgangskrets.
DE69030473T2 (de) Differenzierschaltung
BR9007629A (pt) Peca quebra-cabeca solida-brinquedo logico
DE3785833D1 (de) Logikschaltung.
DE69029363D1 (de) Ausgangsschaltung für eine sourcengekoppelte FET-Logik
FR2608335B1 (fr) Circuit logique cmos
DE69031019T2 (de) Ausgangssteuerungsschaltung
DE68916249T2 (de) Logikschaltung.
DE69022677T2 (de) Logische Schaltung einer sourcegekoppelten FET-Logik.
FR2642885B1 (fr) Echantillonneur-bloqueur hyperfrequence a transistor
IT1232863B (it) Procedimento a ciclo ridotto per la fabbricazione di circuiti stampati, e composizione per la sua attuazione
FI900364A0 (fi) Kolesterolfri salladsdressing.
DE69122184D1 (de) Schwellenfreie logische Schaltung
KR910001747U (ko) 엔모오스 인버터 회로
KR850006789A (ko) 논리회로
DE3852331D1 (de) Kaskaden-FET-Logikschaltungen.
KR910010091U (ko) 고속동작에 적합한 출력단회로
KR880006849A (ko) 논리회로
KR910001745U (ko) 3진 논리 회로
DE68912176D1 (de) Master-Slave-Pufferschaltung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee