DE69213973D1 - SRAM-Zelle mit geschichteter Kapazität - Google Patents
SRAM-Zelle mit geschichteter KapazitätInfo
- Publication number
- DE69213973D1 DE69213973D1 DE69213973T DE69213973T DE69213973D1 DE 69213973 D1 DE69213973 D1 DE 69213973D1 DE 69213973 T DE69213973 T DE 69213973T DE 69213973 T DE69213973 T DE 69213973T DE 69213973 D1 DE69213973 D1 DE 69213973D1
- Authority
- DE
- Germany
- Prior art keywords
- sram cell
- layered
- layered capacitance
- capacitance sram
- capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US64787991A | 1991-01-30 | 1991-01-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69213973D1 true DE69213973D1 (de) | 1996-10-31 |
DE69213973T2 DE69213973T2 (de) | 1997-02-13 |
Family
ID=24598629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69213973T Expired - Fee Related DE69213973T2 (de) | 1991-01-30 | 1992-01-24 | SRAM-Zelle mit geschichteter Kapazität |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0499824B1 (de) |
JP (1) | JP3150184B2 (de) |
KR (1) | KR100232370B1 (de) |
DE (1) | DE69213973T2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3535615B2 (ja) | 1995-07-18 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6642574B2 (en) | 1997-10-07 | 2003-11-04 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
US6169308B1 (en) | 1996-11-15 | 2001-01-02 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
JP3554666B2 (ja) * | 1997-10-07 | 2004-08-18 | 株式会社日立製作所 | 半導体メモリ装置 |
JPH10229135A (ja) | 1997-02-14 | 1998-08-25 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP4753534B2 (ja) * | 2003-12-26 | 2011-08-24 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP4783022B2 (ja) | 2005-01-17 | 2011-09-28 | 株式会社東芝 | 半導体集積回路装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4679171A (en) * | 1985-02-07 | 1987-07-07 | Visic, Inc. | MOS/CMOS memory cell |
US4984200A (en) * | 1987-11-30 | 1991-01-08 | Hitachi, Ltd. | Semiconductor circuit device having a plurality of SRAM type memory cell arrangement |
JPH01152662A (ja) * | 1987-12-09 | 1989-06-15 | Fujitsu Ltd | 半導体記憶装置 |
JP2590171B2 (ja) * | 1988-01-08 | 1997-03-12 | 株式会社日立製作所 | 半導体記憶装置 |
-
1992
- 1992-01-24 EP EP92101131A patent/EP0499824B1/de not_active Expired - Lifetime
- 1992-01-24 DE DE69213973T patent/DE69213973T2/de not_active Expired - Fee Related
- 1992-01-29 KR KR1019920001295A patent/KR100232370B1/ko not_active IP Right Cessation
- 1992-01-30 JP JP01539792A patent/JP3150184B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH06151771A (ja) | 1994-05-31 |
KR100232370B1 (ko) | 1999-12-01 |
DE69213973T2 (de) | 1997-02-13 |
EP0499824A1 (de) | 1992-08-26 |
JP3150184B2 (ja) | 2001-03-26 |
EP0499824B1 (de) | 1996-09-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |