DE69118958D1 - DRAM-Einrichtung mit Zweiweg-Spannungsversorgungssystem - Google Patents

DRAM-Einrichtung mit Zweiweg-Spannungsversorgungssystem

Info

Publication number
DE69118958D1
DE69118958D1 DE69118958T DE69118958T DE69118958D1 DE 69118958 D1 DE69118958 D1 DE 69118958D1 DE 69118958 T DE69118958 T DE 69118958T DE 69118958 T DE69118958 T DE 69118958T DE 69118958 D1 DE69118958 D1 DE 69118958D1
Authority
DE
Germany
Prior art keywords
supply system
voltage supply
dram device
way voltage
way
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69118958T
Other languages
English (en)
Other versions
DE69118958T2 (de
Inventor
Akira Tsujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69118958D1 publication Critical patent/DE69118958D1/de
Publication of DE69118958T2 publication Critical patent/DE69118958T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69118958T 1990-02-13 1991-02-07 DRAM-Einrichtung mit Zweiweg-Spannungsversorgungssystem Expired - Fee Related DE69118958T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2033022A JP3006014B2 (ja) 1990-02-13 1990-02-13 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69118958D1 true DE69118958D1 (de) 1996-05-30
DE69118958T2 DE69118958T2 (de) 1996-09-26

Family

ID=12375171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118958T Expired - Fee Related DE69118958T2 (de) 1990-02-13 1991-02-07 DRAM-Einrichtung mit Zweiweg-Spannungsversorgungssystem

Country Status (5)

Country Link
US (1) US5222044A (de)
EP (1) EP0451453B1 (de)
JP (1) JP3006014B2 (de)
KR (1) KR940003402B1 (de)
DE (1) DE69118958T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5180721A (en) * 1989-05-22 1993-01-19 Allergan, Inc. Combinations of selective alpha-adrenergic agonists and antagonists useful in lowering intraocular pressure
US5281591A (en) * 1989-05-22 1994-01-25 Allergan, Inc. Combinations of selective alpha-adrenergic agonists and antagonists useful in lowering intraocular pressure
US5151440A (en) * 1990-02-28 1992-09-29 Allergan, Inc. Method for reducing or maintaining intraocular pressure in the mammalian eye by administering pharmaceutical compositions containing 2-(2-alkylphenylamino)-oxazolines, 2-(2-alkylphenyl-amino)-thiazolines and 2-(2-alkylphenylamino)-imidazolines
US5252595A (en) * 1990-02-28 1993-10-12 Allergan, Inc. Method for reducing or maintaining intraocular pressure in the mammalian eye by administering pharmaceutical compositions containing 2-(2-alkylphenylamino)-oxazolines, 2-(2-alkylphenylamino)-thiazolines and 2-(2-alkylphenylamino)-imidazolines
JPH04268287A (ja) * 1991-02-22 1992-09-24 Nec Ic Microcomput Syst Ltd 半導体メモリ回路
JP2752304B2 (ja) * 1992-10-21 1998-05-18 株式会社東芝 半導体記憶装置
JPH07230691A (ja) * 1994-02-16 1995-08-29 Fujitsu Ltd 半導体記憶装置
JP3013773B2 (ja) * 1996-03-22 2000-02-28 日本電気株式会社 半導体装置
US6147511A (en) * 1996-05-28 2000-11-14 Altera Corporation Overvoltage-tolerant interface for integrated circuits
US6025737A (en) * 1996-11-27 2000-02-15 Altera Corporation Circuitry for a low internal voltage integrated circuit
US6175952B1 (en) 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US5757712A (en) * 1996-07-12 1998-05-26 International Business Machines Corporation Memory modules with voltage regulation and level translation
KR100432575B1 (ko) * 1997-06-09 2004-07-30 삼성전자주식회사 스태틱 램 장치 및 그것의 감지 증폭 회로
US6239612B1 (en) 1997-08-20 2001-05-29 Altera Corporation Programmable I/O cells with multiple drivers
JP3233911B2 (ja) * 1999-03-17 2001-12-04 株式会社 沖マイクロデザイン 半導体集積回路装置
US6243315B1 (en) 1999-12-31 2001-06-05 James B. Goodman Computer memory system with a low power down mode
JP3866594B2 (ja) 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
KR100682182B1 (ko) 2004-04-12 2007-02-12 주식회사 하이닉스반도체 내부 클럭 더블러 및 이를 포함한 반도체 메모리 장치 및그의 데이터 출력방법
US8174923B2 (en) * 2007-11-08 2012-05-08 Rambus Inc. Voltage-stepped low-power memory device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952497A (ja) * 1982-09-17 1984-03-27 Nec Corp デコ−ダ回路
JPS59151389A (ja) * 1983-02-18 1984-08-29 Hitachi Ltd 大規模集積回路
JPS6196588A (ja) * 1984-10-16 1986-05-15 Mitsubishi Electric Corp 半導体記憶装置
JPS61178795A (ja) * 1985-02-01 1986-08-11 Toshiba Corp ダイナミツク型半導体記憶装置
CA1233565A (en) * 1985-05-28 1988-03-01 Robert A. Penchuk Dynamic mos memory reference voltage generator
US4740921A (en) * 1985-10-04 1988-04-26 Motorola, Inc. Precharge of a dram data line to an intermediate voltage
JPH07111823B2 (ja) * 1986-03-18 1995-11-29 三菱電機株式会社 半導体記憶装置
JPH0713871B2 (ja) * 1987-06-11 1995-02-15 三菱電機株式会社 ダイナミツクｒａｍ
JPH0758593B2 (ja) * 1988-07-06 1995-06-21 松下電器産業株式会社 センスアップ回路

Also Published As

Publication number Publication date
DE69118958T2 (de) 1996-09-26
KR910016000A (ko) 1991-09-30
EP0451453B1 (de) 1996-04-24
KR940003402B1 (ko) 1994-04-21
US5222044A (en) 1993-06-22
EP0451453A1 (de) 1991-10-16
JP3006014B2 (ja) 2000-02-07
JPH03237682A (ja) 1991-10-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee