DE69131972D1 - Speichersteuerungseinheit und Speichereinheit - Google Patents

Speichersteuerungseinheit und Speichereinheit

Info

Publication number
DE69131972D1
DE69131972D1 DE69131972T DE69131972T DE69131972D1 DE 69131972 D1 DE69131972 D1 DE 69131972D1 DE 69131972 T DE69131972 T DE 69131972T DE 69131972 T DE69131972 T DE 69131972T DE 69131972 D1 DE69131972 D1 DE 69131972D1
Authority
DE
Germany
Prior art keywords
memory
address
row
memory bank
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131972T
Other languages
English (en)
Other versions
DE69131972T2 (de
Inventor
James Macdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69131972D1 publication Critical patent/DE69131972D1/de
Publication of DE69131972T2 publication Critical patent/DE69131972T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Vehicle Body Suspensions (AREA)
  • Electrotherapy Devices (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Massaging Devices (AREA)
  • Control Of Eletrric Generators (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Memory System (AREA)
DE69131972T 1990-08-31 1991-07-23 Speichersteuerungseinheit und Speichereinheit Expired - Fee Related DE69131972T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/576,699 US5269010A (en) 1990-08-31 1990-08-31 Memory control for use in a memory system incorporating a plurality of memory banks

Publications (2)

Publication Number Publication Date
DE69131972D1 true DE69131972D1 (de) 2000-03-16
DE69131972T2 DE69131972T2 (de) 2000-10-05

Family

ID=24305600

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131972T Expired - Fee Related DE69131972T2 (de) 1990-08-31 1991-07-23 Speichersteuerungseinheit und Speichereinheit

Country Status (6)

Country Link
US (1) US5269010A (de)
EP (1) EP0473275B1 (de)
JP (1) JPH04245349A (de)
AT (1) ATE189744T1 (de)
DE (1) DE69131972T2 (de)
ES (1) ES2141705T3 (de)

Families Citing this family (37)

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US5644732A (en) * 1990-07-13 1997-07-01 Sun Microsystems, Inc. Method and apparatus for assigning addresses to a computer system's three dimensional packing arrangement
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging
US5446860A (en) * 1993-01-11 1995-08-29 Hewlett-Packard Company Apparatus for determining a computer memory configuration of memory modules using presence detect bits shifted serially into a configuration register
CA2116985C (en) * 1993-03-11 1999-09-21 Cynthia J. Burns Memory system
US5651130A (en) * 1993-03-22 1997-07-22 Compaq Computer Corporation Memory controller that dynamically predicts page misses
US5522069A (en) * 1993-04-30 1996-05-28 Zenith Data Systems Corporation Symmetric multiprocessing system with unified environment and distributed system functions
DE69326236T2 (de) * 1993-06-16 1999-12-30 Bull Hn Information Systems Italia S.P.A., Pregnana Milanese Speicher mit variabeler Verschachtelungshöhe und verwandte Konfigurationseinheit
US5537576A (en) * 1993-06-23 1996-07-16 Dsp Semiconductors Ltd. Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space
US5835952A (en) * 1993-07-14 1998-11-10 Matsushita Electric Industrial Co., Ltd. Monolithic image data memory system and access method that utilizes multiple banks to hide precharge time
US5706407A (en) * 1993-12-28 1998-01-06 Kabushiki Kaisha Toshiba System for reallocation of memory banks in memory sized order
JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
US5721860A (en) * 1994-05-24 1998-02-24 Intel Corporation Memory controller for independently supporting synchronous and asynchronous DRAM memories
FR2721415B1 (fr) * 1994-06-21 1996-09-06 France Telecom Dispositif électronique d'adressage de mémoire, notamment pour une mémoire organisée par bancs.
JPH0822444A (ja) * 1994-07-05 1996-01-23 Matsushita Electric Ind Co Ltd データ転送装置
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5596740A (en) * 1995-01-26 1997-01-21 Cyrix Corporation Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks
US5809539A (en) * 1995-04-27 1998-09-15 Hitachi, Ltd. Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs
JP3075957B2 (ja) * 1995-05-30 2000-08-14 株式会社東芝 コンピュータシステム
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5924111A (en) * 1995-10-17 1999-07-13 Huang; Chu-Kai Method and system for interleaving data in multiple memory bank partitions
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
US5799168A (en) * 1996-01-05 1998-08-25 M-Systems Flash Disk Pioneers Ltd. Standardized flash controller
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US5835932A (en) * 1997-03-13 1998-11-10 Silicon Aquarius, Inc. Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM
US6202133B1 (en) 1997-07-02 2001-03-13 Micron Technology, Inc. Method of processing memory transactions in a computer system having dual system memories and memory controllers
US6049855A (en) * 1997-07-02 2000-04-11 Micron Electronics, Inc. Segmented memory system employing different interleaving scheme for each different memory segment
US6070227A (en) * 1997-10-31 2000-05-30 Hewlett-Packard Company Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
US6226720B1 (en) 1998-12-11 2001-05-01 International Business Machines Corporation Method for optimally configuring memory in a mixed interleave system
DE60012081T2 (de) * 1999-05-11 2004-11-18 Fujitsu Ltd., Kawasaki Nichtflüchtige Halbleiterspeicheranordnung, die eine Datenleseoperation während einer Datenschreib/lösch-Operation erlaubt
US6895488B2 (en) * 2002-05-22 2005-05-17 Lsi Logic Corporation DSP memory bank rotation
US7191342B1 (en) * 2002-06-04 2007-03-13 Xilinx, Inc. Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames
KR100766372B1 (ko) * 2005-11-29 2007-10-11 주식회사 하이닉스반도체 반도체 메모리의 뱅크 제어장치 및 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128450B2 (de) * 1971-10-06 1976-08-19
US4025903A (en) * 1973-09-10 1977-05-24 Computer Automation, Inc. Automatic modular memory address allocation system
IT1142074B (it) * 1981-11-24 1986-10-08 Honeywell Inf Systems Sistema di elaborazione dati con allocazione automatica dell'indirizzo in una memoria modulare
CA1234224A (en) * 1985-05-28 1988-03-15 Boleslav Sykora Computer memory management system
US4926314A (en) * 1987-03-17 1990-05-15 Apple Computer, Inc. Method and apparatus for determining available memory size
US4908789A (en) * 1987-04-01 1990-03-13 International Business Machines Corporation Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US5051889A (en) * 1987-10-23 1991-09-24 Chips And Technologies, Incorporated Page interleaved memory access
US5341486A (en) * 1988-10-27 1994-08-23 Unisys Corporation Automatically variable memory interleaving system
US5129069A (en) * 1989-01-24 1992-07-07 Zenith Data Systems Corporation Method and apparatus for automatic memory configuration by a computer

Also Published As

Publication number Publication date
ATE189744T1 (de) 2000-02-15
EP0473275B1 (de) 2000-02-09
DE69131972T2 (de) 2000-10-05
JPH04245349A (ja) 1992-09-01
US5269010A (en) 1993-12-07
EP0473275A2 (de) 1992-03-04
ES2141705T3 (es) 2000-04-01
EP0473275A3 (en) 1992-04-08

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee