DE69128746T2 - Laserstreckendecodierer für DRAM-Redundanzschema - Google Patents

Laserstreckendecodierer für DRAM-Redundanzschema

Info

Publication number
DE69128746T2
DE69128746T2 DE69128746T DE69128746T DE69128746T2 DE 69128746 T2 DE69128746 T2 DE 69128746T2 DE 69128746 T DE69128746 T DE 69128746T DE 69128746 T DE69128746 T DE 69128746T DE 69128746 T2 DE69128746 T2 DE 69128746T2
Authority
DE
Germany
Prior art keywords
redundancy scheme
laser path
path decoder
dram redundancy
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128746T
Other languages
English (en)
Other versions
DE69128746D1 (de
Inventor
Hiep V Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69128746D1 publication Critical patent/DE69128746D1/de
Publication of DE69128746T2 publication Critical patent/DE69128746T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
DE69128746T 1990-06-19 1991-05-07 Laserstreckendecodierer für DRAM-Redundanzschema Expired - Fee Related DE69128746T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US54025490A 1990-06-19 1990-06-19

Publications (2)

Publication Number Publication Date
DE69128746D1 DE69128746D1 (de) 1998-02-26
DE69128746T2 true DE69128746T2 (de) 1998-07-16

Family

ID=24154664

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128746T Expired - Fee Related DE69128746T2 (de) 1990-06-19 1991-05-07 Laserstreckendecodierer für DRAM-Redundanzschema

Country Status (6)

Country Link
EP (1) EP0469252B1 (de)
JP (1) JP2963789B2 (de)
KR (1) KR920001554A (de)
CN (1) CN1057543A (de)
DE (1) DE69128746T2 (de)
TW (1) TW203147B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19726881A1 (de) 1997-06-24 1999-01-07 Siemens Ag Halbleiterschaltungsvorrichtung und Verfahren zur Herstellung
JPH11260924A (ja) * 1998-03-10 1999-09-24 Mitsubishi Electric Corp 半導体集積回路装置のテスト方法
JP2020178010A (ja) * 2019-04-17 2020-10-29 キオクシア株式会社 半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137192A (ja) * 1981-12-29 1983-08-15 Fujitsu Ltd 半導体記憶装置
JPS593795A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 半導体記憶装置
US4538247A (en) * 1983-01-14 1985-08-27 Fairchild Research Center Redundant rows in integrated circuit memories
EP0213044A3 (de) * 1985-08-20 1989-03-22 STMicroelectronics, Inc. Schaltung zur Ausschaltung von fehlerhaften Elementen mit durch Laser durchgebrannter Sicherung

Also Published As

Publication number Publication date
KR920001554A (ko) 1992-01-30
JP2963789B2 (ja) 1999-10-18
EP0469252B1 (de) 1998-01-21
CN1057543A (zh) 1992-01-01
TW203147B (de) 1993-04-01
JPH04229498A (ja) 1992-08-18
DE69128746D1 (de) 1998-02-26
EP0469252A1 (de) 1992-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee