DE69127320T2 - Integrierte Schaltkreise mit lokaler Bedingungskompensation - Google Patents

Integrierte Schaltkreise mit lokaler Bedingungskompensation

Info

Publication number
DE69127320T2
DE69127320T2 DE69127320T DE69127320T DE69127320T2 DE 69127320 T2 DE69127320 T2 DE 69127320T2 DE 69127320 T DE69127320 T DE 69127320T DE 69127320 T DE69127320 T DE 69127320T DE 69127320 T2 DE69127320 T2 DE 69127320T2
Authority
DE
Germany
Prior art keywords
integrated circuits
local condition
condition compensation
compensation
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127320T
Other languages
English (en)
Other versions
DE69127320D1 (de
Inventor
Masakazu Shoji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69127320D1 publication Critical patent/DE69127320D1/de
Application granted granted Critical
Publication of DE69127320T2 publication Critical patent/DE69127320T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Amplifiers (AREA)
DE69127320T 1990-06-01 1991-05-24 Integrierte Schaltkreise mit lokaler Bedingungskompensation Expired - Fee Related DE69127320T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/531,961 US5117130A (en) 1990-06-01 1990-06-01 Integrated circuits which compensate for local conditions

Publications (2)

Publication Number Publication Date
DE69127320D1 DE69127320D1 (de) 1997-09-25
DE69127320T2 true DE69127320T2 (de) 1998-03-19

Family

ID=24119802

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127320T Expired - Fee Related DE69127320T2 (de) 1990-06-01 1991-05-24 Integrierte Schaltkreise mit lokaler Bedingungskompensation

Country Status (8)

Country Link
US (1) US5117130A (de)
EP (1) EP0459715B1 (de)
JP (1) JPH04230053A (de)
KR (1) KR100219769B1 (de)
DE (1) DE69127320T2 (de)
ES (1) ES2104666T3 (de)
HK (1) HK1001928A1 (de)
SG (1) SG44452A1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247212A (en) * 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family
US5254883A (en) * 1992-04-22 1993-10-19 Rambus, Inc. Electrical current source circuitry for a bus
FR2699023B1 (fr) * 1992-12-09 1995-02-24 Texas Instruments France Circuit à retard commandé.
US5408145A (en) * 1993-02-12 1995-04-18 Advanced Micro Devices, Inc. Low power consumption and high speed NOR gate integrated circuit
KR100302890B1 (ko) * 1993-06-08 2001-11-22 클라크 3세 존 엠. 프로그램가능한cmos버스및전송라인드라이버
US5483184A (en) * 1993-06-08 1996-01-09 National Semiconductor Corporation Programmable CMOS bus and transmission line receiver
US5539341A (en) * 1993-06-08 1996-07-23 National Semiconductor Corporation CMOS bus and transmission line driver having programmable edge rate control
US5557223A (en) * 1993-06-08 1996-09-17 National Semiconductor Corporation CMOS bus and transmission line driver having compensated edge rate control
WO1994029962A1 (en) * 1993-06-08 1994-12-22 National Semiconductor Corporation Cmos btl compatible bus and transmission line driver
US5543746A (en) * 1993-06-08 1996-08-06 National Semiconductor Corp. Programmable CMOS current source having positive temperature coefficient
FR2734378B1 (fr) * 1995-05-17 1997-07-04 Suisse Electronique Microtech Circuit integre dans lequel certains composants fonctionnels sont amenes a travailler avec une meme caracteristique de fonctionnement
US5627456A (en) * 1995-06-07 1997-05-06 International Business Machines Corporation All FET fully integrated current reference circuit
JP2783243B2 (ja) * 1996-02-06 1998-08-06 日本電気株式会社 Ｃｍｏｓ集積回路の故障検出方法及び装置
US5818260A (en) * 1996-04-24 1998-10-06 National Semiconductor Corporation Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay
US6870419B1 (en) 1997-08-29 2005-03-22 Rambus Inc. Memory system including a memory device having a controlled output driver characteristic
US6094075A (en) 1997-08-29 2000-07-25 Rambus Incorporated Current control technique
US6008683A (en) * 1997-10-31 1999-12-28 Credence Systems Corporation Switchable load for testing a semiconductor integrated circuit device
US6188248B1 (en) * 1999-08-26 2001-02-13 Mips Technologies, Inc. Output synchronization-free, high-fanin dynamic NOR gate
US7051130B1 (en) 1999-10-19 2006-05-23 Rambus Inc. Integrated circuit device that stores a value representative of a drive strength setting
US6321282B1 (en) 1999-10-19 2001-11-20 Rambus Inc. Apparatus and method for topography dependent signaling
US6646953B1 (en) * 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US7079775B2 (en) 2001-02-05 2006-07-18 Finisar Corporation Integrated memory mapped controller circuit for fiber optics transceiver
US6396305B1 (en) * 2001-03-29 2002-05-28 Intel Corporation Digital leakage compensation circuit
US7119549B2 (en) 2003-02-25 2006-10-10 Rambus Inc. Output calibrator with dynamic precision
JP4544458B2 (ja) * 2004-11-11 2010-09-15 ルネサスエレクトロニクス株式会社 半導体装置
US7750695B2 (en) * 2004-12-13 2010-07-06 Mosaid Technologies Incorporated Phase-locked loop circuitry using charge pumps with current mirror circuitry
US20080061836A1 (en) * 2006-08-22 2008-03-13 International Business Machines Corporation Current Mirror and Parallel Logic Evaluation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453094A (en) * 1982-06-30 1984-06-05 General Electric Company Threshold amplifier for IC fabrication using CMOS technology
US4714840A (en) * 1982-12-30 1987-12-22 Thomson Components - Mostek Corporation MOS transistor circuits having matched channel width and length dimensions
US4613772A (en) * 1984-04-11 1986-09-23 Harris Corporation Current compensation for logic gates
JPS6320913A (ja) * 1986-07-14 1988-01-28 Nec Corp 出力回路
IT1201848B (it) * 1986-10-02 1989-02-02 Sgs Microelettronica Spa Circuito di interfaccia logica ad alta stabilita' e bassa corrente di riposo
US4763021A (en) * 1987-07-06 1988-08-09 Unisys Corporation CMOS input buffer receiver circuit with ultra stable switchpoint
US4818901A (en) * 1987-07-20 1989-04-04 Harris Corporation Controlled switching CMOS output buffer
US4797580A (en) * 1987-10-29 1989-01-10 Northern Telecom Limited Current-mirror-biased pre-charged logic circuit
US4857767A (en) * 1988-03-03 1989-08-15 Dallas Semiconductor Corporation High-density low-power circuit for sustaining a precharge level
US4857764A (en) * 1988-06-30 1989-08-15 Harris Corporation Current compensated precharged bus

Also Published As

Publication number Publication date
EP0459715B1 (de) 1997-08-20
HK1001928A1 (en) 1998-07-17
DE69127320D1 (de) 1997-09-25
EP0459715A3 (en) 1993-05-19
SG44452A1 (en) 1997-12-19
KR100219769B1 (ko) 1999-09-01
ES2104666T3 (es) 1997-10-16
JPH04230053A (ja) 1992-08-19
US5117130A (en) 1992-05-26
EP0459715A2 (de) 1991-12-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee