DE69124315T2 - Phasenverriegelte Schleifenanordnung mit nichtganzzahligem Mehrfrequenzbezugssignal - Google Patents

Phasenverriegelte Schleifenanordnung mit nichtganzzahligem Mehrfrequenzbezugssignal

Info

Publication number
DE69124315T2
DE69124315T2 DE69124315T DE69124315T DE69124315T2 DE 69124315 T2 DE69124315 T2 DE 69124315T2 DE 69124315 T DE69124315 T DE 69124315T DE 69124315 T DE69124315 T DE 69124315T DE 69124315 T2 DE69124315 T2 DE 69124315T2
Authority
DE
Germany
Prior art keywords
phase
reference signal
locked loop
frequency reference
loop arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69124315T
Other languages
English (en)
Other versions
DE69124315D1 (de
Inventor
Nicholas J Molloy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69124315D1 publication Critical patent/DE69124315D1/de
Application granted granted Critical
Publication of DE69124315T2 publication Critical patent/DE69124315T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
DE69124315T 1990-08-14 1991-08-08 Phasenverriegelte Schleifenanordnung mit nichtganzzahligem Mehrfrequenzbezugssignal Expired - Lifetime DE69124315T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/567,490 US5052031A (en) 1990-08-14 1990-08-14 Phase locked loop including non-integer multiple frequency reference signal

Publications (2)

Publication Number Publication Date
DE69124315D1 DE69124315D1 (de) 1997-03-06
DE69124315T2 true DE69124315T2 (de) 1997-05-15

Family

ID=24267382

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124315T Expired - Lifetime DE69124315T2 (de) 1990-08-14 1991-08-08 Phasenverriegelte Schleifenanordnung mit nichtganzzahligem Mehrfrequenzbezugssignal

Country Status (7)

Country Link
US (1) US5052031A (de)
EP (1) EP0471506B1 (de)
JP (1) JP2593598B2 (de)
KR (1) KR100230512B1 (de)
CA (1) CA2036135C (de)
DE (1) DE69124315T2 (de)
TW (1) TW206298B (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208833A (en) * 1991-04-08 1993-05-04 Motorola, Inc. Multi-level symbol synchronizer
JPH04371024A (ja) * 1991-06-19 1992-12-24 Sony Corp Ｐｌｌ周波数シンセサイザ
US5461717A (en) * 1991-06-21 1995-10-24 Cad Forms Technology Inc. Apparatus for transferring data between a host device and portable computers of various sizes and for recharging the batteries of same
US5268935A (en) * 1991-12-20 1993-12-07 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
JP3241079B2 (ja) * 1992-02-24 2001-12-25 株式会社日立製作所 ディジタル位相同期回路
CA2090523C (en) * 1992-02-29 1998-09-01 Nozomu Watanabe Frequency synthesizer and frequency synthesizing method
US5404172A (en) * 1992-03-02 1995-04-04 Eeg Enterprises, Inc. Video signal data and composite synchronization extraction circuit for on-screen display
US5287296A (en) * 1992-04-22 1994-02-15 At&T Bell Laboratories Clock generators having programmable fractional frequency division
US5398263A (en) * 1993-01-14 1995-03-14 Motorola, Inc. Autonomous pulse train timing controls for time-mark alignment
US5424881A (en) 1993-02-01 1995-06-13 Cirrus Logic, Inc. Synchronous read channel
AU6339594A (en) * 1993-06-09 1994-12-15 Alcatel N.V. Synchronized clock
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
US5646564A (en) * 1994-09-02 1997-07-08 Xilinx, Inc. Phase-locked delay loop for clock correction
US5982210A (en) * 1994-09-02 1999-11-09 Sun Microsystems, Inc. PLL system clock generator with instantaneous clock frequency shifting
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
US5768573A (en) * 1996-11-20 1998-06-16 International Business Machines Corporation Method and apparatus for computing a real time clock divisor
FR2757001B1 (fr) * 1996-12-05 1999-02-05 Sgs Thomson Microelectronics Dispositif de decoupage de la periode d'un signal en n parties quasi-egales
JPH10262021A (ja) * 1997-03-17 1998-09-29 Fujitsu Ltd 伝送装置
US5920216A (en) * 1997-04-03 1999-07-06 Advanced Micro Devices, Inc. Method and system for generating digital clock signals of programmable frequency employing programmable delay lines
EP1012980B1 (de) * 1997-07-10 2002-03-06 Nokia Networks Oy Digitaler phase locked loop
DE19729476C2 (de) * 1997-07-10 2000-04-27 Nokia Networks Oy Numerisch gesteuerter Oszillator
DE19729477A1 (de) * 1997-07-10 1999-02-11 Nokia Telecommunications Oy Digitaler Phase Locked Loop
US6661863B1 (en) 1999-04-16 2003-12-09 Infineon Technologies North America Corp. Phase mixer
US6408419B1 (en) 1999-07-01 2002-06-18 Infineon Technologies North America Corp. Trellis code for extended partial response maximum likelihood (EPRML) channel
US6831963B2 (en) * 2000-10-20 2004-12-14 University Of Central Florida EUV, XUV, and X-Ray wavelength sources created from laser plasma produced from liquid metal solutions
US6356134B1 (en) 2000-03-21 2002-03-12 International Business Machines Corporation Universal clock generator circuit and adjustment method for providing a plurality of clock frequencies
US6845457B1 (en) 2000-09-26 2005-01-18 Sun Microsystems, Inc. Method and apparatus for controlling transitions between a first and a second clock frequency
US6728890B1 (en) 2000-09-26 2004-04-27 Sun Microsystems, Inc. Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component
US6691215B1 (en) * 2000-09-26 2004-02-10 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
US6748546B1 (en) 2000-09-26 2004-06-08 Sun Microsystems, Inc. Method and apparatus for reducing power consumption
EP1244214A1 (de) * 2001-03-23 2002-09-25 STMicroelectronics Limited Phasengesteuerter digitaler Frequenzteiler
US6882662B2 (en) * 2001-06-07 2005-04-19 Applied Micro Circuits Corporation Pointer adjustment wander and jitter reduction apparatus for a desynchronizer
KR100423155B1 (ko) * 2001-12-15 2004-03-16 엘지전자 주식회사 디피-피엘엘의 지터 감쇠 장치 및 방법
DE102004046404B4 (de) * 2004-09-24 2006-07-20 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Bestimmen einer Frequenzdrift in einem Phasenregelkreis
DE102005022126B4 (de) * 2005-05-12 2008-10-02 Siemens Ag Verfahren zum Ermitteln eines Ansteueralgorithmus für einen Zähler zur Bildung eines Taktsignals sowie Zähler- und Steueranordnungen zur Ansteuerung des Zählers
US7675332B1 (en) 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US7586344B1 (en) * 2007-10-16 2009-09-08 Lattice Semiconductor Corporation Dynamic delay or advance adjustment of oscillating signal phase
CN110324040A (zh) * 2019-05-06 2019-10-11 杭州阿姆科技有限公司 一种时钟频率调整的方法及装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057568A (de) * 1973-09-21 1975-05-20
US3936762A (en) * 1974-06-17 1976-02-03 The Charles Stark Draper Laboratory, Inc. Digital phase-lock loop systems for phase processing of signals
US4030045A (en) * 1976-07-06 1977-06-14 International Telephone And Telegraph Corporation Digital double differential phase-locked loop
US4363002A (en) * 1980-11-13 1982-12-07 Fuller Robert M Clock recovery apparatus for phase shift keyed encoded data
JPS57173230A (en) * 1981-04-17 1982-10-25 Hitachi Ltd Phase synchronizing circuit
US4569063A (en) * 1983-06-22 1986-02-04 Gte Automatic Electric Incorporated Digital phase locking arrangement for synchronizing digital span data
JPS6242633A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd ユニバ−サル・デイジタルクロツク抽出回路
US4712224A (en) * 1986-10-09 1987-12-08 Rockwell International Corporation Offset digitally controlled oscillator
US4847875A (en) * 1987-02-26 1989-07-11 American Telephone And Telegraph Company Timing circuit including jitter compensation
DE3719582C2 (de) * 1987-06-12 1999-01-28 Philips Broadcast Television S Schaltungsanordnung zur Erzeugung eines Phasenreferenzsignals
JPH01243621A (ja) * 1988-03-24 1989-09-28 Nec Corp ディジタル位相同期発振器
JPH02231831A (ja) * 1989-03-06 1990-09-13 Hitachi Ltd デジタルａｆｃ回路

Also Published As

Publication number Publication date
EP0471506A2 (de) 1992-02-19
KR100230512B1 (ko) 1999-11-15
JPH04234225A (ja) 1992-08-21
KR920005502A (ko) 1992-03-28
DE69124315D1 (de) 1997-03-06
CA2036135C (en) 1997-01-07
JP2593598B2 (ja) 1997-03-26
EP0471506A3 (en) 1992-12-09
TW206298B (de) 1993-05-21
US5052031A (en) 1991-09-24
CA2036135A1 (en) 1992-02-15
EP0471506B1 (de) 1997-01-22

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