DE69120333T2 - Verriegeltes On-Chip-Fehlererkennungs- und -korrektursystem - Google Patents

Verriegeltes On-Chip-Fehlererkennungs- und -korrektursystem

Info

Publication number
DE69120333T2
DE69120333T2 DE69120333T DE69120333T DE69120333T2 DE 69120333 T2 DE69120333 T2 DE 69120333T2 DE 69120333 T DE69120333 T DE 69120333T DE 69120333 T DE69120333 T DE 69120333T DE 69120333 T2 DE69120333 T2 DE 69120333T2
Authority
DE
Germany
Prior art keywords
locked
error detection
correction system
chip error
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69120333T
Other languages
English (en)
Other versions
DE69120333D1 (de
Inventor
John Atkinson Fifield
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69120333D1 publication Critical patent/DE69120333D1/de
Publication of DE69120333T2 publication Critical patent/DE69120333T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69120333T 1990-04-16 1991-03-01 Verriegeltes On-Chip-Fehlererkennungs- und -korrektursystem Expired - Lifetime DE69120333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/517,896 US5307356A (en) 1990-04-16 1990-04-16 Interlocked on-chip ECC system

Publications (2)

Publication Number Publication Date
DE69120333D1 DE69120333D1 (de) 1996-07-25
DE69120333T2 true DE69120333T2 (de) 1997-01-23

Family

ID=24061680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120333T Expired - Lifetime DE69120333T2 (de) 1990-04-16 1991-03-01 Verriegeltes On-Chip-Fehlererkennungs- und -korrektursystem

Country Status (4)

Country Link
US (2) US5307356A (de)
EP (1) EP0452649B1 (de)
JP (1) JP2571317B2 (de)
DE (1) DE69120333T2 (de)

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US5559453A (en) * 1995-09-28 1996-09-24 International Business Machines Corporation Interlocked restore circuit
US5604755A (en) * 1995-11-20 1997-02-18 International Business Machine Corp. Memory system reset circuit
US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US5784391A (en) * 1996-10-08 1998-07-21 International Business Machines Corporation Distributed memory system with ECC and method of operation
US5926227A (en) * 1997-07-28 1999-07-20 Lsi Logic Corporation Video decoder dynamic memory allocation system and method with error recovery
EP0917059A1 (de) * 1997-11-14 1999-05-19 Nec Corporation Halbleiterspeicheranordnung mit einer Fehlerkorrekturkodeschaltung
US6543029B1 (en) * 1999-09-29 2003-04-01 Emc Corporation Error corrector
US6654925B1 (en) 2000-08-29 2003-11-25 International Business Machines Corporation Method to determine retries for parallel ECC correction in a pipeline
US6400619B1 (en) 2001-04-25 2002-06-04 International Business Machines Corporation Micro-cell redundancy scheme for high performance eDRAM
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US20030115538A1 (en) * 2001-12-13 2003-06-19 Micron Technology, Inc. Error correction in ROM embedded DRAM
JP3914839B2 (ja) * 2002-07-11 2007-05-16 エルピーダメモリ株式会社 半導体記憶装置
US20040148559A1 (en) * 2003-01-23 2004-07-29 Fetzer Eric S. Method and circuit for reducing silent data corruption in storage arrays with no increase in read and write times
JP2005203064A (ja) * 2004-01-19 2005-07-28 Toshiba Corp 半導体記憶装置
US7341765B2 (en) * 2004-01-27 2008-03-11 Battelle Energy Alliance, Llc Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7512861B2 (en) * 2004-05-20 2009-03-31 Vladimir Brajovic Method for determining identity of simultaneous events and applications to image sensing and A/D conversion
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) * 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US20080096631A1 (en) * 2004-10-02 2008-04-24 Wms Gaming Inc. Gaming Device With Error Correcting Memory
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
US7644341B2 (en) * 2004-12-30 2010-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for correcting soft errors in memory circuit
US20060265636A1 (en) * 2005-05-19 2006-11-23 Klaus Hummler Optimized testing of on-chip error correction circuit
JP4768374B2 (ja) * 2005-09-16 2011-09-07 株式会社東芝 半導体記憶装置
US7894289B2 (en) * 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) * 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US20080168331A1 (en) * 2007-01-05 2008-07-10 Thomas Vogelsang Memory including error correction code circuit
US7805658B2 (en) * 2007-02-12 2010-09-28 International Business Machines Corporation DRAM Cache with on-demand reload
US7840876B2 (en) * 2007-02-20 2010-11-23 Qimonda Ag Power savings for memory with error correction mode
TW200842869A (en) * 2007-04-24 2008-11-01 Nanya Technology Corp Control method for read operation of memory
US9471418B2 (en) * 2007-06-19 2016-10-18 Samsung Electronics Co., Ltd. Memory system that detects bit errors due to read disturbance and methods thereof
JP2009070509A (ja) * 2007-09-14 2009-04-02 Oki Electric Ind Co Ltd 半導体記憶装置
JP2009238094A (ja) * 2008-03-28 2009-10-15 Hitachi Ltd ストレージシステム及びデータ保存方法
JP2010020839A (ja) * 2008-07-10 2010-01-28 Panasonic Corp 半導体記憶装置
US8364896B2 (en) * 2008-09-20 2013-01-29 Freescale Semiconductor, Inc. Method and apparatus for configuring a unified cache based on an associated error rate
KR102143517B1 (ko) 2013-02-26 2020-08-12 삼성전자 주식회사 에러 정정회로를 포함하는 반도체 메모리 장치 및 반도체 메모리 장치의 동작방법
US9740558B2 (en) 2015-05-31 2017-08-22 Intel Corporation On-die ECC with error counter and internal address generation
US9842021B2 (en) 2015-08-28 2017-12-12 Intel Corporation Memory device check bit read mode
US9997233B1 (en) 2015-10-08 2018-06-12 Rambus Inc. Memory module with dynamic stripe width

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IT1202527B (it) * 1987-02-12 1989-02-09 Honeywell Inf Systems Sistema di memoria e relativo apparato di rivelazione-correzione di errore
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Also Published As

Publication number Publication date
US5307356A (en) 1994-04-26
EP0452649B1 (de) 1996-06-19
JPH04222999A (ja) 1992-08-12
JP2571317B2 (ja) 1997-01-16
EP0452649A3 (en) 1993-02-24
US5638385A (en) 1997-06-10
DE69120333D1 (de) 1996-07-25
EP0452649A2 (de) 1991-10-23

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