DE69119828T2 - Halbleiteranordnung mit einem isolierenden Graben und Verfahren zu deren Herstellung - Google Patents
Halbleiteranordnung mit einem isolierenden Graben und Verfahren zu deren HerstellungInfo
- Publication number
- DE69119828T2 DE69119828T2 DE1991619828 DE69119828T DE69119828T2 DE 69119828 T2 DE69119828 T2 DE 69119828T2 DE 1991619828 DE1991619828 DE 1991619828 DE 69119828 T DE69119828 T DE 69119828T DE 69119828 T2 DE69119828 T2 DE 69119828T2
- Authority
- DE
- Germany
- Prior art keywords
- production
- semiconductor device
- insulating trench
- trench
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66371—Thyristors structurally associated with another device, e.g. built-in diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/7412—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode
- H01L29/7416—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode the device being an antiparallel diode, e.g. RCT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Element Separation (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2154621A JP2547468B2 (ja) | 1990-06-12 | 1990-06-12 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69119828D1 DE69119828D1 (de) | 1996-07-04 |
DE69119828T2 true DE69119828T2 (de) | 1997-01-02 |
Family
ID=15588186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1991619828 Expired - Fee Related DE69119828T2 (de) | 1990-06-12 | 1991-06-12 | Halbleiteranordnung mit einem isolierenden Graben und Verfahren zu deren Herstellung |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0461879B1 (de) |
JP (1) | JP2547468B2 (de) |
DE (1) | DE69119828T2 (de) |
ES (1) | ES2087245T3 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2796057B2 (ja) * | 1993-03-25 | 1998-09-10 | 三菱電機株式会社 | 逆導通ゲートターンオフサイリスタ |
KR100695868B1 (ko) | 2005-06-23 | 2007-03-19 | 삼성전자주식회사 | 소자 분리막과 그 제조 방법, 이를 갖는 반도체 장치 및 그제조 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57147276A (en) * | 1981-03-06 | 1982-09-11 | Hitachi Ltd | Reverse conductive type semiconductor switching device |
JPS57148371A (en) * | 1981-03-10 | 1982-09-13 | Nec Corp | Manufacture of mesa type semiconductor device |
DE3521079A1 (de) * | 1984-06-12 | 1985-12-12 | Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa | Rueckwaerts leitende vollsteuergate-thyristoranordnung |
DE3422051C2 (de) * | 1984-06-14 | 1986-06-26 | Brown, Boveri & Cie Ag, 6800 Mannheim | Silizium-Halbleiterbauelement mit ätztechnisch hergestellter Randkontur und Verfahren zur Herstellung dieses Bauelements |
CH668505A5 (de) * | 1985-03-20 | 1988-12-30 | Bbc Brown Boveri & Cie | Halbleiterbauelement. |
EP0286855A1 (de) * | 1987-04-15 | 1988-10-19 | BBC Brown Boveri AG | Verfahren zum Aetzen von Vertiefungen in ein Siliziumsubstrat |
-
1990
- 1990-06-12 JP JP2154621A patent/JP2547468B2/ja not_active Expired - Lifetime
-
1991
- 1991-06-12 ES ES91305303T patent/ES2087245T3/es not_active Expired - Lifetime
- 1991-06-12 EP EP19910305303 patent/EP0461879B1/de not_active Expired - Lifetime
- 1991-06-12 DE DE1991619828 patent/DE69119828T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0445579A (ja) | 1992-02-14 |
EP0461879A2 (de) | 1991-12-18 |
JP2547468B2 (ja) | 1996-10-23 |
DE69119828D1 (de) | 1996-07-04 |
EP0461879A3 (en) | 1992-12-16 |
ES2087245T3 (es) | 1996-07-16 |
EP0461879B1 (de) | 1996-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |