DE69118511D1 - EPROM und Verfahren zur Herstellung - Google Patents

EPROM und Verfahren zur Herstellung

Info

Publication number
DE69118511D1
DE69118511D1 DE69118511T DE69118511T DE69118511D1 DE 69118511 D1 DE69118511 D1 DE 69118511D1 DE 69118511 T DE69118511 T DE 69118511T DE 69118511 T DE69118511 T DE 69118511T DE 69118511 D1 DE69118511 D1 DE 69118511D1
Authority
DE
Germany
Prior art keywords
eprom
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69118511T
Other languages
English (en)
Inventor
Noriaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69118511D1 publication Critical patent/DE69118511D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69118511T 1990-12-20 1991-12-20 EPROM und Verfahren zur Herstellung Expired - Lifetime DE69118511D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP40424690 1990-12-20

Publications (1)

Publication Number Publication Date
DE69118511D1 true DE69118511D1 (de) 1996-05-09

Family

ID=18513936

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118511T Expired - Lifetime DE69118511D1 (de) 1990-12-20 1991-12-20 EPROM und Verfahren zur Herstellung

Country Status (4)

Country Link
US (2) US5498891A (de)
EP (1) EP0503205B1 (de)
KR (1) KR970000533B1 (de)
DE (1) DE69118511D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0694211B1 (de) * 1994-02-17 2001-06-20 National Semiconductor Corporation Verfahren zur reduzierung den abstandes zwischen den horizontalen benachbarten schwebenden gates einer flash eprom anordnung
US5556799A (en) * 1995-11-13 1996-09-17 United Microelectronics Corporation Process for fabricating a flash EEPROM
DE19604260C2 (de) 1996-02-06 1998-04-30 Siemens Ag Festwert-Speicherzellenvorrichtung und ein Verfahren zu deren Herstellung
JP3523746B2 (ja) 1996-03-14 2004-04-26 株式会社東芝 半導体記憶装置の製造方法
US6097072A (en) * 1996-03-28 2000-08-01 Advanced Micro Devices Trench isolation with suppressed parasitic edge transistors
JP4027447B2 (ja) * 1996-04-24 2007-12-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US5914514A (en) * 1996-09-27 1999-06-22 Xilinx, Inc. Two transistor flash EPROM cell
US5830789A (en) * 1996-11-19 1998-11-03 Integrated Device Technology, Inc. CMOS process forming wells after gate formation
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6002160A (en) 1997-12-12 1999-12-14 Advanced Micro Devices, Inc. Semiconductor isolation process to minimize weak oxide problems
JP3528575B2 (ja) * 1998-02-17 2004-05-17 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
US6066530A (en) * 1998-04-09 2000-05-23 Advanced Micro Devices, Inc. Oxygen implant self-aligned, floating gate and isolation structure
JP4334036B2 (ja) * 1998-07-31 2009-09-16 株式会社東芝 不揮発性半導体記憶装置
US6228713B1 (en) * 1999-06-28 2001-05-08 Chartered Semiconductor Manufacturing Ltd. Self-aligned floating gate for memory application using shallow trench isolation
JP2001230390A (ja) * 2000-02-17 2001-08-24 Mitsubishi Electric Corp 半導体不揮発性記憶装置およびその製造法
KR100381850B1 (ko) * 2000-08-29 2003-04-26 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성방법
US6700154B1 (en) 2002-09-20 2004-03-02 Lattice Semiconductor Corporation EEPROM cell with trench coupling capacitor
JP4000087B2 (ja) * 2003-05-07 2007-10-31 株式会社東芝 半導体装置およびその製造方法
US7628932B2 (en) 2006-06-02 2009-12-08 Micron Technology, Inc. Wet etch suitable for creating square cuts in si
US7625776B2 (en) * 2006-06-02 2009-12-01 Micron Technology, Inc. Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon
US7709341B2 (en) * 2006-06-02 2010-05-04 Micron Technology, Inc. Methods of shaping vertical single crystal silicon walls and resulting structures
DE102010061763A1 (de) 2010-11-23 2012-05-24 Sb Limotive Germany Gmbh Verfahren zum Laden einer Batterie
US8847319B2 (en) 2012-03-09 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for multiple gate dielectric interface and methods
US9362272B2 (en) 2012-11-01 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral MOSFET

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326331A (en) * 1979-09-17 1982-04-27 Texas Instruments Incorporated High coupling ratio electrically programmable ROM
FR2562326B1 (fr) * 1984-03-30 1987-01-23 Bois Daniel Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre
US4713677A (en) * 1985-02-28 1987-12-15 Texas Instruments Incorporated Electrically erasable programmable read only memory cell including trench capacitor
JPS6231177A (ja) * 1985-08-02 1987-02-10 Nec Corp 不揮発性半導体記憶装置
JPS62163376A (ja) * 1986-01-14 1987-07-20 Fujitsu Ltd 半導体記憶装置の製造方法
US4835115A (en) * 1987-12-07 1989-05-30 Texas Instruments Incorporated Method for forming oxide-capped trench isolation
JPH02168674A (ja) * 1988-12-21 1990-06-28 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5045489A (en) * 1989-06-30 1991-09-03 Texas Instruments Incorporated Method of making a high-speed 2-transistor cell for programmable/EEPROM devices with separate read and write transistors
JPH088313B2 (ja) * 1989-07-25 1996-01-29 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US5051795A (en) * 1989-11-21 1991-09-24 Texas Instruments Incorporated EEPROM with trench-isolated bitlines
JPH05326978A (ja) * 1992-05-21 1993-12-10 Rohm Co Ltd 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
KR970000533B1 (ko) 1997-01-13
EP0503205A3 (en) 1993-02-24
EP0503205B1 (de) 1996-04-03
US5498891A (en) 1996-03-12
US5731237A (en) 1998-03-24
KR920013729A (ko) 1992-07-29
EP0503205A2 (de) 1992-09-16

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