DE69114175D1 - Verfahren zur Herstellung von einer Maske und einem Dünnschichttransistor. - Google Patents

Verfahren zur Herstellung von einer Maske und einem Dünnschichttransistor.

Info

Publication number
DE69114175D1
DE69114175D1 DE69114175T DE69114175T DE69114175D1 DE 69114175 D1 DE69114175 D1 DE 69114175D1 DE 69114175 T DE69114175 T DE 69114175T DE 69114175 T DE69114175 T DE 69114175T DE 69114175 D1 DE69114175 D1 DE 69114175D1
Authority
DE
Germany
Prior art keywords
mask
production
thin film
film transistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114175T
Other languages
English (en)
Other versions
DE69114175T2 (de
Inventor
George Edward Possin
Siegfried Aftergut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of DE69114175D1 publication Critical patent/DE69114175D1/de
Application granted granted Critical
Publication of DE69114175T2 publication Critical patent/DE69114175T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE69114175T 1990-04-17 1991-04-10 Verfahren zur Herstellung von einer Maske und einem Dünnschichttransistor. Expired - Fee Related DE69114175T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/510,767 US5130263A (en) 1990-04-17 1990-04-17 Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer

Publications (2)

Publication Number Publication Date
DE69114175D1 true DE69114175D1 (de) 1995-12-07
DE69114175T2 DE69114175T2 (de) 1996-06-05

Family

ID=24032112

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114175T Expired - Fee Related DE69114175T2 (de) 1990-04-17 1991-04-10 Verfahren zur Herstellung von einer Maske und einem Dünnschichttransistor.

Country Status (6)

Country Link
US (1) US5130263A (de)
EP (1) EP0453169B1 (de)
JP (1) JP3045804B2 (de)
KR (1) KR0185402B1 (de)
CN (1) CN1032233C (de)
DE (1) DE69114175T2 (de)

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KR940007451B1 (ko) * 1991-09-06 1994-08-18 주식회사 금성사 박막트랜지스터 제조방법
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WO1994020982A1 (en) * 1993-03-01 1994-09-15 General Electric Company Self-aligned thin-film transistor constructed using lift-off technique
KR100263900B1 (ko) * 1993-03-04 2000-09-01 윤종용 마스크 및 그 제조방법
US5384271A (en) * 1993-10-04 1995-01-24 General Electric Company Method for reduction of off-current in thin film transistors
KR970004429B1 (ko) * 1993-10-29 1997-03-27 현대전자산업 주식회사 위상 반전 마스크 및 그 제조 방법
KR0128827B1 (ko) * 1993-12-31 1998-04-07 김주용 위상반전마스크 제조방법
KR970005675B1 (en) * 1994-01-19 1997-04-18 Hyundai Electronics Ind Fabrication method of phase shift mask
KR950026032A (ko) * 1994-02-25 1995-09-18 김광호 다결정실리콘 박막트랜지스터의 제조방법
FR2719416B1 (fr) * 1994-04-29 1996-07-05 Thomson Lcd Procédé de passivation des flancs d'un composant semiconducteur à couches minces.
JP3176527B2 (ja) * 1995-03-30 2001-06-18 シャープ株式会社 半導体装置の製造方法
US5612235A (en) * 1995-11-01 1997-03-18 Industrial Technology Research Institute Method of making thin film transistor with light-absorbing layer
JP3516424B2 (ja) * 1996-03-10 2004-04-05 株式会社半導体エネルギー研究所 薄膜半導体装置
US5637519A (en) * 1996-03-21 1997-06-10 Industrial Technology Research Institute Method of fabricating a lightly doped drain thin-film transistor
KR100202236B1 (ko) * 1996-04-09 1999-07-01 구자홍 액티브 매트릭스 기판의 제조방법 및 그 방법에 의해 제조되는 액티브 매트릭스 기판
JPH1050607A (ja) * 1996-07-31 1998-02-20 Sony Corp 半導体装置の製造方法
KR100569729B1 (ko) * 1997-04-07 2006-08-10 삼성전자주식회사 소스 및 드레인용 금속으로 몰리브덴 텅스텐 합금을 사용하는 박막 트랜지스터 액정 표시 소자 기판 및 그 제조 방법
US6395624B1 (en) 1999-02-22 2002-05-28 International Business Machines Corporation Method for forming implants in semiconductor fabrication
US6184069B1 (en) * 1999-05-24 2001-02-06 Chi Mei Electronics Corp. Fabrication of thin film transistor-liquid crystal display with self-aligned transparent conducting layers
US6790599B1 (en) * 1999-07-15 2004-09-14 Microbionics, Inc. Microfluidic devices and manufacture thereof
GB0021030D0 (en) * 2000-08-26 2000-10-11 Koninkl Philips Electronics Nv A method of forming a bottom-gate thin film transistor
US6642085B1 (en) 2000-11-03 2003-11-04 The Regents Of The University Of California Thin film transistors on plastic substrates with reflective coatings for radiation protection
US7262070B2 (en) * 2003-09-29 2007-08-28 Intel Corporation Method to make a weight compensating/tuning layer on a substrate
JP2005173037A (ja) * 2003-12-09 2005-06-30 Fujitsu Display Technologies Corp 液晶表示装置及びその製造方法
US7223641B2 (en) * 2004-03-26 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for manufacturing the same, liquid crystal television and EL television
KR100701088B1 (ko) * 2004-10-26 2007-03-29 비오이 하이디스 테크놀로지 주식회사 프린지 필드 스위칭 모드 액정표시장치의 제조방법
TWI272725B (en) * 2005-04-15 2007-02-01 Quanta Display Inc Method of fabricating TFT array substrate and metal layer thereof
KR100685936B1 (ko) * 2005-06-27 2007-02-22 엘지.필립스 엘시디 주식회사 Ｉｐｓ모드 액정표시소자 및 그 제조방법
US8187480B2 (en) * 2008-11-13 2012-05-29 Seagate Technology, Llc Ultra thin alignment walls for di-block copolymer
JP5960430B2 (ja) * 2011-12-23 2016-08-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR101951707B1 (ko) * 2012-02-14 2019-02-26 삼성디스플레이 주식회사 기판의 평탄화 방법, 상기 평탄화 방법을 이용한 박막 트랜지스터의 제조 방법
KR101960796B1 (ko) * 2012-03-08 2019-07-16 삼성디스플레이 주식회사 박막 트랜지스터의 제조 방법, 표시 기판의 제조 방법 및 표시 기판
CN103345119B (zh) * 2013-07-04 2015-03-25 苏州华博电子科技有限公司 一种带接地孔的陶瓷薄膜电路光刻方法
CN105206678A (zh) * 2015-10-29 2015-12-30 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制作方法
CN105655257A (zh) * 2016-01-13 2016-06-08 深圳市华星光电技术有限公司 薄膜晶体管结构的制造方法
CN105895534B (zh) * 2016-06-15 2018-10-19 武汉华星光电技术有限公司 薄膜晶体管的制备方法
CN107221563A (zh) * 2017-05-10 2017-09-29 陕西师范大学 一种底栅自对准结构金属氧化物薄膜晶体管及其制备方法
JP2019054150A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置の製造方法および半導体ウェハ
KR102084493B1 (ko) * 2019-02-19 2020-03-05 삼성디스플레이 주식회사 기판의 평탄화 방법, 상기 평탄화 방법을 이용한 박막 트랜지스터의 제조 방법

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US4332879A (en) * 1978-12-01 1982-06-01 Hughes Aircraft Company Process for depositing a film of controlled composition using a metallo-organic photoresist
DE3128949A1 (de) * 1981-07-22 1983-02-10 Basf Ag, 6700 Ludwigshafen Lichtempfindliche aufzeichnungsmaterialien zur herstellung von abriebs- und kratzfesten tiefdruckformen sowie verfahren zur herstellung von tiefdruckformen mittels dieser aufzeichnungsmaterialien
EP0075537B2 (de) * 1981-09-17 1991-03-20 Ciba-Geigy Ag Verfahren zum Beschichten gedruckter Schaltungen
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JPS60223121A (ja) * 1984-04-19 1985-11-07 Matsushita Electric Ind Co Ltd パタ−ン形成方法
JPS60224223A (ja) * 1984-04-20 1985-11-08 Nec Corp Ｘ線露光方法
JPS61279862A (ja) * 1985-06-06 1986-12-10 Fuji Photo Film Co Ltd 画像形成方法
JPH01173650A (ja) * 1987-12-26 1989-07-10 Seikosha Co Ltd 非晶質シリコン薄膜トランジスタの製造方法
JPH0634401B2 (ja) * 1987-12-29 1994-05-02 株式会社精工舎 遮光性薄膜のエッチング方法
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US5010027A (en) * 1990-03-21 1991-04-23 General Electric Company Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure

Also Published As

Publication number Publication date
US5130263A (en) 1992-07-14
JPH05165053A (ja) 1993-06-29
EP0453169A2 (de) 1991-10-23
EP0453169A3 (en) 1991-12-27
KR0185402B1 (ko) 1999-04-15
JP3045804B2 (ja) 2000-05-29
CN1032233C (zh) 1996-07-03
EP0453169B1 (de) 1995-11-02
DE69114175T2 (de) 1996-06-05
CN1056187A (zh) 1991-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: ROEGER UND KOLLEGEN, 73728 ESSLINGEN

8339 Ceased/non-payment of the annual fee