DE69110999T2 - Dynamische Pufferschaltung. - Google Patents

Dynamische Pufferschaltung.

Info

Publication number
DE69110999T2
DE69110999T2 DE69110999T DE69110999T DE69110999T2 DE 69110999 T2 DE69110999 T2 DE 69110999T2 DE 69110999 T DE69110999 T DE 69110999T DE 69110999 T DE69110999 T DE 69110999T DE 69110999 T2 DE69110999 T2 DE 69110999T2
Authority
DE
Germany
Prior art keywords
buffer circuit
dynamic buffer
dynamic
circuit
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69110999T
Other languages
English (en)
Other versions
DE69110999D1 (de
Inventor
Takashi Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69110999D1 publication Critical patent/DE69110999D1/de
Publication of DE69110999T2 publication Critical patent/DE69110999T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69110999T 1990-08-29 1991-08-29 Dynamische Pufferschaltung. Expired - Fee Related DE69110999T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2227712A JP2788783B2 (ja) 1990-08-29 1990-08-29 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69110999D1 DE69110999D1 (de) 1995-08-10
DE69110999T2 true DE69110999T2 (de) 1995-12-07

Family

ID=16865172

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69110999T Expired - Fee Related DE69110999T2 (de) 1990-08-29 1991-08-29 Dynamische Pufferschaltung.

Country Status (4)

Country Link
US (1) US5208480A (de)
EP (1) EP0475637B1 (de)
JP (1) JP2788783B2 (de)
DE (1) DE69110999T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151775A (en) * 1991-10-07 1992-09-29 Tektronix, Inc. Integrated circuit device having improved substrate capacitance isolation
US6898613B1 (en) * 1999-08-26 2005-05-24 Stmicroelectronics, Inc. Arithmetic circuits for use with the residue number system
US6822908B1 (en) * 2003-05-08 2004-11-23 Micron Technology, Inc. Synchronous up/down address generator for burst mode read
JP6389954B2 (ja) * 2015-03-26 2018-09-12 富士フイルム株式会社 電子回路装置および電子回路装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068639A (ja) * 1983-08-31 1985-04-19 Toshiba Corp 樹脂封止型半導体装置
JPS60134440A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体集積回路装置
EP0154346B1 (de) * 1984-03-08 1991-09-18 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltungsvorrichtung
JPS6164166A (ja) * 1984-09-06 1986-04-02 Toshiba Corp 半導体装置
JPH0666442B2 (ja) * 1985-03-08 1994-08-24 三菱電機株式会社 半導体メモリ装置
JPS6267851A (ja) * 1985-09-20 1987-03-27 Hitachi Ltd 半導体集積回路装置
JPS63160241A (ja) * 1986-12-24 1988-07-04 Toshiba Corp スタンダ−ドセル方式の半導体集積回路
JPH01191512A (ja) * 1988-01-27 1989-08-01 Seiko Epson Corp ラッチ回路
JPH01251738A (ja) * 1988-03-31 1989-10-06 Toshiba Corp スタンダードセル
JPH0750708B2 (ja) * 1989-04-26 1995-05-31 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
EP0475637A3 (en) 1992-05-27
EP0475637B1 (de) 1995-07-05
JP2788783B2 (ja) 1998-08-20
JPH04109624A (ja) 1992-04-10
EP0475637A2 (de) 1992-03-18
US5208480A (en) 1993-05-04
DE69110999D1 (de) 1995-08-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee