DE69110500T2 - Halbleiterspeicherschaltungsanordnung mit Gate-Array-Speicherzellen. - Google Patents

Halbleiterspeicherschaltungsanordnung mit Gate-Array-Speicherzellen.

Info

Publication number
DE69110500T2
DE69110500T2 DE69110500T DE69110500T DE69110500T2 DE 69110500 T2 DE69110500 T2 DE 69110500T2 DE 69110500 T DE69110500 T DE 69110500T DE 69110500 T DE69110500 T DE 69110500T DE 69110500 T2 DE69110500 T2 DE 69110500T2
Authority
DE
Germany
Prior art keywords
gate array
circuit arrangement
memory cells
semiconductor memory
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69110500T
Other languages
English (en)
Other versions
DE69110500D1 (de
Inventor
Hiroyuki Hara
Yoshinori Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69110500D1 publication Critical patent/DE69110500D1/de
Publication of DE69110500T2 publication Critical patent/DE69110500T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE69110500T 1990-02-28 1991-02-28 Halbleiterspeicherschaltungsanordnung mit Gate-Array-Speicherzellen. Expired - Fee Related DE69110500T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2045518A JP2791167B2 (ja) 1990-02-28 1990-02-28 半導体記憶回路装置

Publications (2)

Publication Number Publication Date
DE69110500D1 DE69110500D1 (de) 1995-07-27
DE69110500T2 true DE69110500T2 (de) 1996-01-25

Family

ID=12721638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69110500T Expired - Fee Related DE69110500T2 (de) 1990-02-28 1991-02-28 Halbleiterspeicherschaltungsanordnung mit Gate-Array-Speicherzellen.

Country Status (5)

Country Link
US (1) US5289405A (de)
EP (1) EP0444687B1 (de)
JP (1) JP2791167B2 (de)
KR (1) KR940004403B1 (de)
DE (1) DE69110500T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69314360T2 (de) * 1992-01-22 1998-01-29 Samsung Semiconductor Inc Nichtinvertierendes logisches Tor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH079978B2 (ja) * 1987-02-24 1995-02-01 富士通株式会社 マスタスライス型半導体集積回路
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit
JPH0350766A (ja) * 1989-07-18 1991-03-05 Nec Corp バイポーラｃｍｏｓゲートアレイ半導体装置

Also Published As

Publication number Publication date
EP0444687B1 (de) 1995-06-21
EP0444687A3 (en) 1992-08-05
KR940004403B1 (ko) 1994-05-25
DE69110500D1 (de) 1995-07-27
EP0444687A2 (de) 1991-09-04
US5289405A (en) 1994-02-22
KR920000073A (ko) 1992-01-10
JP2791167B2 (ja) 1998-08-27
JPH03250664A (ja) 1991-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee