DE69100017D1 - Schaltung zur pruefung von elektrisch programmierbaren speicherzellen. - Google Patents
Schaltung zur pruefung von elektrisch programmierbaren speicherzellen.Info
- Publication number
- DE69100017D1 DE69100017D1 DE9191401591T DE69100017T DE69100017D1 DE 69100017 D1 DE69100017 D1 DE 69100017D1 DE 9191401591 T DE9191401591 T DE 9191401591T DE 69100017 T DE69100017 T DE 69100017T DE 69100017 D1 DE69100017 D1 DE 69100017D1
- Authority
- DE
- Germany
- Prior art keywords
- input
- output
- read
- electrically programmable
- situated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9007792A FR2663774B1 (fr) | 1990-06-21 | 1990-06-21 | Circuit de test de cellules memoires electriquement programmables. |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69100017D1 true DE69100017D1 (de) | 1993-02-11 |
DE69100017T2 DE69100017T2 (de) | 1993-04-29 |
Family
ID=9397875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE9191401591T Expired - Fee Related DE69100017T2 (de) | 1990-06-21 | 1991-06-14 | Schaltung zur pruefung von elektrisch programmierbaren speicherzellen. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5291448A (de) |
EP (1) | EP0462876B1 (de) |
DE (1) | DE69100017T2 (de) |
FR (1) | FR2663774B1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5455517A (en) * | 1992-06-09 | 1995-10-03 | International Business Machines Corporation | Data output impedance control |
DE69326329T2 (de) * | 1993-06-28 | 2000-04-13 | Stmicroelectronics S.R.L., Agrate Brianza | Speicherzellen-Stromleseverfahren in Mikrosteuergerät |
US5675539A (en) * | 1994-12-21 | 1997-10-07 | Sgs-Thomson Microelectronics, S.A. | Method and circuit for testing memories in integrated circuit form |
FR2728717B1 (fr) * | 1994-12-21 | 1997-01-31 | Sgs Thomson Microelectronics | Procede et circuit de test pour memoire en circuit integre |
ITMI20021583A1 (it) * | 2002-07-18 | 2004-01-19 | St Microelectronics Srl | Metodo di decodifica automatica per la mappatura e la selezione di undispositivo di memoria non volatile con un'interfaccia seriale di comu |
US7114032B2 (en) * | 2003-07-18 | 2006-09-26 | International Business Machines Corporation | Method and system for efficient fragment caching |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4301535A (en) * | 1979-07-02 | 1981-11-17 | Mostek Corporation | Programmable read only memory integrated circuit with bit-check and deprogramming modes and methods for programming and testing said circuit |
JPH0658947B2 (ja) * | 1984-02-24 | 1994-08-03 | 株式会社日立製作所 | 半導体メモリ装置の製法 |
JPH0632222B2 (ja) * | 1987-01-14 | 1994-04-27 | 日本電気アイシーマイコンシステム株式会社 | ラツチ回路 |
FR2623653B1 (fr) * | 1987-11-24 | 1992-10-23 | Sgs Thomson Microelectronics | Procede de test de cellules de memoire electriquement programmable et circuit integre correspondant |
FR2636464B1 (fr) * | 1988-09-14 | 1990-10-26 | Sgs Thomson Microelectronics | Memoire eprom avec signature interne concernant notamment le mode de programmation |
US5157627A (en) * | 1990-07-17 | 1992-10-20 | Crosscheck Technology, Inc. | Method and apparatus for setting desired signal level on storage element |
-
1990
- 1990-06-21 FR FR9007792A patent/FR2663774B1/fr not_active Expired - Fee Related
-
1991
- 1991-06-14 EP EP91401591A patent/EP0462876B1/de not_active Expired - Lifetime
- 1991-06-14 DE DE9191401591T patent/DE69100017T2/de not_active Expired - Fee Related
- 1991-06-21 US US07/718,627 patent/US5291448A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2663774A1 (fr) | 1991-12-27 |
DE69100017T2 (de) | 1993-04-29 |
EP0462876B1 (de) | 1992-12-30 |
FR2663774B1 (fr) | 1992-09-25 |
EP0462876A1 (de) | 1991-12-27 |
US5291448A (en) | 1994-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |