DE69032382D1 - Digitale Signalverarbeitungsschaltung - Google Patents

Digitale Signalverarbeitungsschaltung

Info

Publication number
DE69032382D1
DE69032382D1 DE69032382T DE69032382T DE69032382D1 DE 69032382 D1 DE69032382 D1 DE 69032382D1 DE 69032382 T DE69032382 T DE 69032382T DE 69032382 T DE69032382 T DE 69032382T DE 69032382 D1 DE69032382 D1 DE 69032382D1
Authority
DE
Germany
Prior art keywords
signal processing
digital signal
processing circuit
circuit
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032382T
Other languages
English (en)
Other versions
DE69032382T2 (de
Inventor
Tadao Fujita
Yoshiaki Inaba
Jun Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69032382D1 publication Critical patent/DE69032382D1/de
Application granted granted Critical
Publication of DE69032382T2 publication Critical patent/DE69032382T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1497—Details of time redundant execution on a single processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/18—Conversion to or from residue codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
DE69032382T 1989-07-29 1990-07-27 Digitale Signalverarbeitungsschaltung Expired - Fee Related DE69032382T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1197593A JP2930325B2 (ja) 1989-07-29 1989-07-29 ディジタル信号処理回路

Publications (2)

Publication Number Publication Date
DE69032382D1 true DE69032382D1 (de) 1998-07-16
DE69032382T2 DE69032382T2 (de) 1998-10-08

Family

ID=16377068

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032382T Expired - Fee Related DE69032382T2 (de) 1989-07-29 1990-07-27 Digitale Signalverarbeitungsschaltung

Country Status (5)

Country Link
US (1) US5117383A (de)
EP (1) EP0411504B1 (de)
JP (1) JP2930325B2 (de)
KR (1) KR100248448B1 (de)
DE (1) DE69032382T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987487A (en) * 1996-03-11 1999-11-16 Cirrus Logic, Inc. Methods and apparatus for the processing of digital signals
US5892632A (en) * 1996-11-18 1999-04-06 Cirrus Logic, Inc. Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery
US7523151B1 (en) * 2000-05-12 2009-04-21 The Athena Group, Inc. Method and apparatus for performing computations using residue arithmetic
KR20020069591A (ko) * 2001-02-26 2002-09-05 디브이테크놀로지 모듈로 머젠수 아날로그 디지트 병렬 승산기 및 그 기술의응용방법
JP2008282178A (ja) * 2007-05-09 2008-11-20 Toshiba Corp 産業用コントローラ
US20140139365A1 (en) * 2011-06-30 2014-05-22 Chan Hua Vun System for rns based analog-to-digital conversion and inner product computation
US9026506B2 (en) * 2012-04-02 2015-05-05 University Of North Texas System and method for multi-residue multivariate data compression
US9081608B2 (en) * 2012-05-19 2015-07-14 Digital System Research Inc. Residue number arithmetic logic unit
US9712185B2 (en) * 2012-05-19 2017-07-18 Olsen Ip Reserve, Llc System and method for improved fractional binary to fractional residue converter and multipler
US10296292B2 (en) * 2016-10-20 2019-05-21 Advanced Micro Devices, Inc. Dynamic variable precision computation
IT201700008949A1 (it) * 2017-01-27 2018-07-27 St Microelectronics Srl Procedimento di funzionamento di reti neurali, rete, apparecchiatura e prodotto informatico corrispondenti
US10387122B1 (en) 2018-05-04 2019-08-20 Olsen Ip Reserve, Llc Residue number matrix multiplier
US10992314B2 (en) 2019-01-21 2021-04-27 Olsen Ip Reserve, Llc Residue number systems and methods for arithmetic error detection and correction
WO2021124413A1 (ja) * 2019-12-16 2021-06-24 三菱電機株式会社 フィルタ装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1353213A (en) * 1971-09-27 1974-05-15 Rosemount Eng Co Ltd Digital data processing equipment and to control systems using digital data processing
US4041284A (en) * 1976-09-07 1977-08-09 The United States Of America As Represented By The Secretary Of The Navy Signal processing devices using residue class arithmetic
JPS56158525A (en) * 1980-05-12 1981-12-07 Nec Corp Circulation type digital filter
GB2077008B (en) * 1980-05-21 1985-02-06 Slechta Jiri Mathematical convergency in digital computers
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals
SU1166116A1 (ru) * 1984-01-13 1985-07-07 Институт математики и механики АН КазССР Устройство дл обнаружени ошибок в слабоарифметическом коде системы остаточных классов
EP0166563A3 (de) * 1984-06-21 1987-07-15 Texas Instruments Incorporated Universaler Digitalfilter in Restklassenzahlensystemen
US4598266A (en) * 1984-09-24 1986-07-01 Gte Communications Systems Corporation Modulo adder
US4831576A (en) * 1986-05-06 1989-05-16 Yamaha Corporation Multiplier circuit
US4949293A (en) * 1987-09-25 1990-08-14 Kabushiki Kaisha Toshiba Method and apparatus for computing residue with respect to arbitrary modulus
JPH0199325A (ja) * 1987-10-12 1989-04-18 Sony Corp エンコーダ回路
JP2699358B2 (ja) * 1987-11-12 1998-01-19 ソニー株式会社 デコーダ回路
FR2622713A1 (fr) * 1987-10-30 1989-05-05 Thomson Csf Circuit de calcul utilisant une arithmetique residuelle
JPH01120111A (ja) * 1987-11-02 1989-05-12 Yokogawa Electric Corp ディジタルフィルタ
US4910699A (en) * 1988-08-18 1990-03-20 The Boeing Company Optical computer including parallel residue to binary conversion

Also Published As

Publication number Publication date
EP0411504B1 (de) 1998-06-10
EP0411504A3 (en) 1993-02-03
KR100248448B1 (ko) 2000-03-15
JP2930325B2 (ja) 1999-08-03
EP0411504A2 (de) 1991-02-06
JPH0360509A (ja) 1991-03-15
DE69032382T2 (de) 1998-10-08
KR910003504A (ko) 1991-02-27
US5117383A (en) 1992-05-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee