DE69030409D1 - Herstellungsverfahren für eine selbstjustierte diffundierte Verbindungsstruktur - Google Patents

Herstellungsverfahren für eine selbstjustierte diffundierte Verbindungsstruktur

Info

Publication number
DE69030409D1
DE69030409D1 DE69030409T DE69030409T DE69030409D1 DE 69030409 D1 DE69030409 D1 DE 69030409D1 DE 69030409 T DE69030409 T DE 69030409T DE 69030409 T DE69030409 T DE 69030409T DE 69030409 D1 DE69030409 D1 DE 69030409D1
Authority
DE
Germany
Prior art keywords
self
manufacturing process
connection structure
diffused connection
aligned diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69030409T
Other languages
English (en)
Other versions
DE69030409T2 (de
Inventor
Peter J Zdebel
Barbara Vasquez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69030409D1 publication Critical patent/DE69030409D1/de
Application granted granted Critical
Publication of DE69030409T2 publication Critical patent/DE69030409T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69030409T 1989-07-21 1990-07-16 Herstellungsverfahren für eine selbstjustierte diffundierte Verbindungsstruktur Expired - Fee Related DE69030409T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/382,879 US5026663A (en) 1989-07-21 1989-07-21 Method of fabricating a structure having self-aligned diffused junctions

Publications (2)

Publication Number Publication Date
DE69030409D1 true DE69030409D1 (de) 1997-05-15
DE69030409T2 DE69030409T2 (de) 1997-10-23

Family

ID=23510780

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69030409T Expired - Fee Related DE69030409T2 (de) 1989-07-21 1990-07-16 Herstellungsverfahren für eine selbstjustierte diffundierte Verbindungsstruktur

Country Status (4)

Country Link
US (1) US5026663A (de)
EP (1) EP0409132B1 (de)
JP (1) JPH0370127A (de)
DE (1) DE69030409T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397912A (en) * 1991-12-02 1995-03-14 Motorola, Inc. Lateral bipolar transistor
US5156987A (en) * 1991-12-18 1992-10-20 Micron Technology, Inc. High performance thin film transistor (TFT) by solid phase epitaxial regrowth
US5331116A (en) * 1992-04-30 1994-07-19 Sgs-Thomson Microelectronics, Inc. Structure and method for forming contact structures in integrated circuits
US5650655A (en) 1994-04-28 1997-07-22 Micron Technology, Inc. Integrated circuitry having electrical interconnects
US5493130A (en) * 1993-06-10 1996-02-20 Micron Technology, Inc. Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers
JP2679647B2 (ja) * 1994-09-28 1997-11-19 日本電気株式会社 半導体装置
US5844297A (en) * 1995-09-26 1998-12-01 Symbios, Inc. Antifuse device for use on a field programmable interconnect chip
KR100255512B1 (ko) * 1996-06-29 2000-05-01 김영환 플래쉬 메모리 소자 제조방법
US6387768B1 (en) * 2000-08-29 2002-05-14 Semiconductor Components Industries Llc Method of manufacturing a semiconductor component and semiconductor component thereof
US6809396B2 (en) * 2002-11-25 2004-10-26 Semiconductor Components Industries, L.L.C. Integrated circuit with a high speed narrow base width vertical PNP transistor
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US7232732B2 (en) * 2003-10-06 2007-06-19 Atmel Corporation Semiconductor device with a toroidal-like junction
US20050239250A1 (en) * 2003-08-11 2005-10-27 Bohumil Lojek Ultra dense non-volatile memory array
US7169660B2 (en) * 2003-10-06 2007-01-30 Atmel Corporation Lithography-independent fabrication of small openings for forming vertical mos transistor
US7300850B2 (en) * 2005-09-30 2007-11-27 Semiconductor Components Industries, L.L.C. Method of forming a self-aligned transistor
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits
US20070235797A1 (en) * 2006-03-29 2007-10-11 Bohumil Lojek Process for reducing a size of a compact EEPROM device
JP2013001435A (ja) * 2011-06-17 2013-01-07 Nitto Lifetech Kk 袋体構成部材用多孔質フィルム及びカイロ用袋体構成部材

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4333794A (en) * 1981-04-07 1982-06-08 International Business Machines Corporation Omission of thick Si3 N4 layers in ISA schemes
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
US4545114A (en) * 1982-09-30 1985-10-08 Fujitsu Limited Method of producing semiconductor device
NL8302541A (nl) * 1983-07-15 1985-02-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US4569701A (en) * 1984-04-05 1986-02-11 At&T Bell Laboratories Technique for doping from a polysilicon transfer layer
JPH0658912B2 (ja) * 1985-05-07 1994-08-03 日本電信電話株式会社 バイポーラトランジスタの製造方法
US4678537A (en) * 1985-05-23 1987-07-07 Sony Corporation Method of manufacturing semiconductor devices
JPS63193562A (ja) * 1987-02-06 1988-08-10 Toshiba Corp バイポ−ラトランジスタの製造方法
US4839305A (en) * 1988-06-28 1989-06-13 Texas Instruments Incorporated Method of making single polysilicon self-aligned transistor

Also Published As

Publication number Publication date
EP0409132A3 (en) 1991-11-21
JPH0370127A (ja) 1991-03-26
US5026663A (en) 1991-06-25
EP0409132A2 (de) 1991-01-23
DE69030409T2 (de) 1997-10-23
EP0409132B1 (de) 1997-04-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee