DE69025841D1 - Verfahren für die Überwachung von Fehlanpassungsversetzungen - Google Patents

Verfahren für die Überwachung von Fehlanpassungsversetzungen

Info

Publication number
DE69025841D1
DE69025841D1 DE69025841T DE69025841T DE69025841D1 DE 69025841 D1 DE69025841 D1 DE 69025841D1 DE 69025841 T DE69025841 T DE 69025841T DE 69025841 T DE69025841 T DE 69025841T DE 69025841 D1 DE69025841 D1 DE 69025841D1
Authority
DE
Germany
Prior art keywords
mismatch
transfers
procedures
monitoring
monitoring mismatch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025841T
Other languages
English (en)
Other versions
DE69025841T2 (de
Inventor
Katsuhiko Miki
Yukio Naruke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69025841D1 publication Critical patent/DE69025841D1/de
Application granted granted Critical
Publication of DE69025841T2 publication Critical patent/DE69025841T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/127—Process induced defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69025841T 1989-09-29 1990-09-27 Verfahren für die Überwachung von Fehlanpassungsversetzungen Expired - Fee Related DE69025841T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1253822A JPH03116820A (ja) 1989-09-29 1989-09-29 ミスフィット転位制御方法

Publications (2)

Publication Number Publication Date
DE69025841D1 true DE69025841D1 (de) 1996-04-18
DE69025841T2 DE69025841T2 (de) 1996-08-01

Family

ID=17256621

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025841T Expired - Fee Related DE69025841T2 (de) 1989-09-29 1990-09-27 Verfahren für die Überwachung von Fehlanpassungsversetzungen

Country Status (4)

Country Link
US (1) US5395770A (de)
EP (1) EP0420636B1 (de)
JP (1) JPH03116820A (de)
DE (1) DE69025841T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6236079B1 (en) * 1997-12-02 2001-05-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having a trench capacitor
US6100150A (en) * 1998-09-04 2000-08-08 Taiwan Semiconductor Manufacturing Company Process to improve temperature uniformity during RTA by deposition of in situ poly on the wafer backside
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density
KR101119019B1 (ko) * 2004-12-14 2012-03-12 주식회사 엘지실트론 질화갈륨 반도체 및 이의 제조 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3923567A (en) * 1974-08-09 1975-12-02 Silicon Materials Inc Method of reclaiming a semiconductor wafer
US4131487A (en) * 1977-10-26 1978-12-26 Western Electric Company, Inc. Gettering semiconductor wafers with a high energy laser beam
JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
JPS55124236A (en) * 1979-03-19 1980-09-25 Mitsubishi Electric Corp Semiconductor substrate
US4257827A (en) * 1979-11-13 1981-03-24 International Business Machines Corporation High efficiency gettering in silicon through localized superheated melt formation
JPS5671929A (en) * 1979-11-16 1981-06-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Treatment for silicon substrate
JPS5671928A (en) * 1979-11-16 1981-06-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Treatment for silicon substrate
JPS5680139A (en) * 1979-12-05 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS56129698A (en) * 1980-03-11 1981-10-09 Nec Corp Crystal growing method
JPS57153438A (en) * 1981-03-18 1982-09-22 Nec Corp Manufacture of semiconductor substrate
US4525239A (en) * 1984-04-23 1985-06-25 Hewlett-Packard Company Extrinsic gettering of GaAs wafers for MESFETS and integrated circuits
JPS61156820A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 半導体装置の製造方法
US4659400A (en) * 1985-06-27 1987-04-21 General Instrument Corp. Method for forming high yield epitaxial wafers
EP0251280A3 (de) * 1986-06-30 1989-11-23 Nec Corporation Laserverfahren zur Getterung für Halbleiterscheiben
JPS63192227A (ja) * 1987-02-05 1988-08-09 Seiko Instr & Electronics Ltd 化合物半導体のエピタキシヤル成長方法
US4878988A (en) * 1988-10-03 1989-11-07 Motorola, Inc. Gettering process for semiconductor wafers
JPH0472735A (ja) * 1990-07-13 1992-03-06 Mitsubishi Materials Corp 半導体ウエーハのゲッタリング方法

Also Published As

Publication number Publication date
EP0420636A1 (de) 1991-04-03
US5395770A (en) 1995-03-07
JPH03116820A (ja) 1991-05-17
EP0420636B1 (de) 1996-03-13
DE69025841T2 (de) 1996-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee