DE69025795D1 - Ultrahöchstintegrierte Schaltungsbauweise mit linearen Verbindungen - Google Patents

Ultrahöchstintegrierte Schaltungsbauweise mit linearen Verbindungen

Info

Publication number
DE69025795D1
DE69025795D1 DE69025795T DE69025795T DE69025795D1 DE 69025795 D1 DE69025795 D1 DE 69025795D1 DE 69025795 T DE69025795 T DE 69025795T DE 69025795 T DE69025795 T DE 69025795T DE 69025795 D1 DE69025795 D1 DE 69025795D1
Authority
DE
Germany
Prior art keywords
ultra
integrated circuit
circuit design
high integrated
linear connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025795T
Other languages
English (en)
Other versions
DE69025795T2 (de
Inventor
Robert W Horst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of DE69025795D1 publication Critical patent/DE69025795D1/de
Application granted granted Critical
Publication of DE69025795T2 publication Critical patent/DE69025795T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69025795T 1989-05-02 1990-05-02 Ultrahöchstintegrierte Schaltungsbauweise mit linearen Verbindungen Expired - Fee Related DE69025795T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/346,203 US5203005A (en) 1989-05-02 1989-05-02 Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement

Publications (2)

Publication Number Publication Date
DE69025795D1 true DE69025795D1 (de) 1996-04-18
DE69025795T2 DE69025795T2 (de) 1996-08-22

Family

ID=23358389

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025795T Expired - Fee Related DE69025795T2 (de) 1989-05-02 1990-05-02 Ultrahöchstintegrierte Schaltungsbauweise mit linearen Verbindungen

Country Status (6)

Country Link
US (2) US5203005A (de)
EP (1) EP0398552B1 (de)
JP (1) JPH0369138A (de)
AU (1) AU638454B2 (de)
CA (1) CA2015853A1 (de)
DE (1) DE69025795T2 (de)

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DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
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US6294926B1 (en) 1999-07-16 2001-09-25 Philips Electronics North America Corporation Very fine-grain field programmable gate array architecture and circuitry
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US6671837B1 (en) * 2000-06-06 2003-12-30 Intel Corporation Device and method to test on-chip memory in a production environment
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
ATE437476T1 (de) 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
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US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
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Also Published As

Publication number Publication date
EP0398552B1 (de) 1996-03-13
CA2015853A1 (en) 1990-11-02
JPH0369138A (ja) 1991-03-25
DE69025795T2 (de) 1996-08-22
EP0398552A2 (de) 1990-11-22
AU638454B2 (en) 1993-07-01
US5287472A (en) 1994-02-15
US5203005A (en) 1993-04-13
EP0398552A3 (de) 1992-03-25
AU5470890A (en) 1990-11-08

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee