DE69021036D1 - Test-Anordnungssystem für integrierte Schaltungen unter Verwendung von lateralen Transistoren. - Google Patents

Test-Anordnungssystem für integrierte Schaltungen unter Verwendung von lateralen Transistoren.

Info

Publication number
DE69021036D1
DE69021036D1 DE69021036T DE69021036T DE69021036D1 DE 69021036 D1 DE69021036 D1 DE 69021036D1 DE 69021036 T DE69021036 T DE 69021036T DE 69021036 T DE69021036 T DE 69021036T DE 69021036 D1 DE69021036 D1 DE 69021036D1
Authority
DE
Germany
Prior art keywords
integrated circuits
test arrangement
arrangement system
lateral transistors
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021036T
Other languages
English (en)
Other versions
DE69021036T2 (de
Inventor
Vance R Harwood
Kevin W Keirn
John J Keller
Ronald J Peiffer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69021036D1 publication Critical patent/DE69021036D1/de
Publication of DE69021036T2 publication Critical patent/DE69021036T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
DE69021036T 1990-01-31 1990-11-27 Test-Anordnungssystem für integrierte Schaltungen unter Verwendung von lateralen Transistoren. Expired - Fee Related DE69021036T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/472,926 US5101152A (en) 1990-01-31 1990-01-31 Integrated circuit transfer test device system utilizing lateral transistors

Publications (2)

Publication Number Publication Date
DE69021036D1 true DE69021036D1 (de) 1995-08-24
DE69021036T2 DE69021036T2 (de) 1995-11-30

Family

ID=23877458

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021036T Expired - Fee Related DE69021036T2 (de) 1990-01-31 1990-11-27 Test-Anordnungssystem für integrierte Schaltungen unter Verwendung von lateralen Transistoren.

Country Status (4)

Country Link
US (1) US5101152A (de)
EP (1) EP0439922B1 (de)
JP (1) JP3195800B2 (de)
DE (1) DE69021036T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557209A (en) * 1990-12-20 1996-09-17 Hewlett-Packard Company Identification of pin-open faults by capacitive coupling through the integrated circuit package
US5625292A (en) * 1990-12-20 1997-04-29 Hewlett-Packard Company System for measuring the integrity of an electrical contact
DE4110551C1 (de) * 1991-03-30 1992-07-23 Ita Ingenieurbuero Fuer Testaufgaben Gmbh, 2000 Hamburg, De
US5225816A (en) * 1991-08-12 1993-07-06 Motorola, Inc. Electrical connector with display
IT1259395B (it) * 1992-05-29 1996-03-13 Luciano Bonaria Metodo di rilevamento di connesioni erronee in schede elettroniche
US5420500A (en) * 1992-11-25 1995-05-30 Hewlett-Packard Company Pacitive electrode system for detecting open solder joints in printed circuit assemblies
US5818251A (en) * 1996-06-11 1998-10-06 National Semiconductor Corporation Apparatus and method for testing the connections between an integrated circuit and a printed circuit board
DE19733113B4 (de) * 1997-07-31 2008-01-31 OCé PRINTING SYSTEMS GMBH Verfahren zum Testen einer elektronischen Baugruppe und elektronische Baugruppe mit Testhilfe
JP4174167B2 (ja) * 2000-04-04 2008-10-29 株式会社アドバンテスト 半導体集積回路の故障解析方法および故障解析装置
ES2641583T3 (es) 2007-04-16 2017-11-10 Marquardt Gmbh Procedimiento para la fabricación de un interruptor electromecánico
CN113009266B (zh) * 2021-03-18 2024-06-21 广州亚美智造科技有限公司 一种治具插拔检测电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3335340A (en) * 1964-02-24 1967-08-08 Ibm Combined transistor and testing structures and fabrication thereof
US3622883A (en) * 1965-08-18 1971-11-23 Ibm Pulsed current transistor beta tester having feedback to maintain emitter to collector current constant
US3774088A (en) * 1972-12-29 1973-11-20 Ibm An integrated circuit test transistor structure and method of fabricating the same
CA997481A (en) * 1972-12-29 1976-09-21 International Business Machines Corporation Dc testing of integrated circuits and a novel integrated circuit structure to facilitate such testing
US3889188A (en) * 1973-07-30 1975-06-10 Ibm Time zero determination of FET reliability
US4042832A (en) * 1975-12-29 1977-08-16 Honeywell Information Systems Inc. Logic board interlock indication apparatus
DE2840981C2 (de) * 1977-10-08 1984-03-29 Tokyo Electric Co., Ltd., Tokyo Speichereinsatz für elektronische Registrierkassen und Datenverarbeitungseinheiten
EP0075079A1 (de) * 1981-09-21 1983-03-30 International Business Machines Corporation Schaltungsnetzwerkkontrollsystem
GB8428405D0 (en) * 1984-11-09 1984-12-19 Membrain Ltd Automatic test equipment
US4864219A (en) * 1987-03-19 1989-09-05 Genrad, Inc. Method and apparatus for verifying proper placement of integrated circuits on circuit boards
US4779041A (en) * 1987-05-20 1988-10-18 Hewlett-Packard Company Integrated circuit transfer test device system
US4801878A (en) * 1987-06-18 1989-01-31 Hewlett-Packard Company In-circuit transistor beta test and method
US4894605A (en) * 1988-02-24 1990-01-16 Digital Equipment Corporation Method and on-chip apparatus for continuity testing
US4896108A (en) * 1988-07-25 1990-01-23 American Telephone And Telegraph Company, At&T Bell Laboratories Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits

Also Published As

Publication number Publication date
DE69021036T2 (de) 1995-11-30
EP0439922B1 (de) 1995-07-19
JPH04213077A (ja) 1992-08-04
JP3195800B2 (ja) 2001-08-06
EP0439922A2 (de) 1991-08-07
EP0439922A3 (en) 1992-04-29
US5101152A (en) 1992-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee