DE69020220D1 - Direktspeicherzugriff zwischen unterschiedlichen Bussystemen mit Cachespeicherübereinstimmung. - Google Patents

Direktspeicherzugriff zwischen unterschiedlichen Bussystemen mit Cachespeicherübereinstimmung.

Info

Publication number
DE69020220D1
DE69020220D1 DE69020220T DE69020220T DE69020220D1 DE 69020220 D1 DE69020220 D1 DE 69020220D1 DE 69020220 T DE69020220 T DE 69020220T DE 69020220 T DE69020220 T DE 69020220T DE 69020220 D1 DE69020220 D1 DE 69020220D1
Authority
DE
Germany
Prior art keywords
bus systems
different bus
match
cache memory
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69020220T
Other languages
English (en)
Other versions
DE69020220T2 (de
Inventor
John G Theus
Jeffrey L Beachy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23310606&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69020220(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Tektronix Inc filed Critical Tektronix Inc
Application granted granted Critical
Publication of DE69020220D1 publication Critical patent/DE69020220D1/de
Publication of DE69020220T2 publication Critical patent/DE69020220T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69020220T 1989-04-07 1990-03-06 Direktspeicherzugriff zwischen unterschiedlichen Bussystemen mit Cachespeicherübereinstimmung. Expired - Fee Related DE69020220T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/335,173 US5072369A (en) 1989-04-07 1989-04-07 Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates

Publications (2)

Publication Number Publication Date
DE69020220D1 true DE69020220D1 (de) 1995-07-27
DE69020220T2 DE69020220T2 (de) 1996-04-04

Family

ID=23310606

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69020220T Expired - Fee Related DE69020220T2 (de) 1989-04-07 1990-03-06 Direktspeicherzugriff zwischen unterschiedlichen Bussystemen mit Cachespeicherübereinstimmung.

Country Status (3)

Country Link
US (1) US5072369A (de)
EP (1) EP0392657B1 (de)
DE (1) DE69020220T2 (de)

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US5446848A (en) * 1993-06-25 1995-08-29 Unisys Corp Entry level data processing system which is expandable by a factor of two to a partitionable upgraded system with low overhead
US5623633A (en) * 1993-07-27 1997-04-22 Dell Usa, L.P. Cache-based computer system employing a snoop control circuit with write-back suppression
US5630095A (en) * 1993-08-03 1997-05-13 Motorola Inc. Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor
US5526512A (en) * 1993-09-20 1996-06-11 International Business Machines Corporation Dynamic management of snoop granularity for a coherent asynchronous DMA cache
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US5797026A (en) * 1994-02-28 1998-08-18 Intel Corporation Method and apparatus for self-snooping a bus during a boundary transaction
US5572702A (en) * 1994-02-28 1996-11-05 Intel Corporation Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
US5835742A (en) * 1994-06-14 1998-11-10 Apple Computer, Inc. System and method for executing indivisible memory operations in multiple processor computer systems with multiple busses
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US5634073A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
US5630094A (en) * 1995-01-20 1997-05-13 Intel Corporation Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
US5893921A (en) * 1995-02-10 1999-04-13 International Business Machines Corporation Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller
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Also Published As

Publication number Publication date
EP0392657B1 (de) 1995-06-21
EP0392657A1 (de) 1990-10-17
DE69020220T2 (de) 1996-04-04
US5072369A (en) 1991-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee