ATE170642T1 - Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien - Google Patents

Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien

Info

Publication number
ATE170642T1
ATE170642T1 AT91305422T AT91305422T ATE170642T1 AT E170642 T1 ATE170642 T1 AT E170642T1 AT 91305422 T AT91305422 T AT 91305422T AT 91305422 T AT91305422 T AT 91305422T AT E170642 T1 ATE170642 T1 AT E170642T1
Authority
AT
Austria
Prior art keywords
level cache
cache controller
data
level
caches
Prior art date
Application number
AT91305422T
Other languages
English (en)
Inventor
Roger E Tipley
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of ATE170642T1 publication Critical patent/ATE170642T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
AT91305422T 1990-06-15 1991-06-14 Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien ATE170642T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53889490A 1990-06-15 1990-06-15

Publications (1)

Publication Number Publication Date
ATE170642T1 true ATE170642T1 (de) 1998-09-15

Family

ID=24148867

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91305422T ATE170642T1 (de) 1990-06-15 1991-06-14 Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien

Country Status (6)

Country Link
US (1) US5369753A (de)
EP (1) EP0461926B1 (de)
JP (1) JPH04233048A (de)
AT (1) ATE170642T1 (de)
CA (1) CA2044689A1 (de)
DE (1) DE69130086T2 (de)

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Also Published As

Publication number Publication date
JPH04233048A (ja) 1992-08-21
EP0461926B1 (de) 1998-09-02
CA2044689A1 (en) 1991-12-16
EP0461926A2 (de) 1991-12-18
DE69130086T2 (de) 1999-01-21
US5369753A (en) 1994-11-29
EP0461926A3 (en) 1992-05-06
DE69130086D1 (de) 1998-10-08

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