DE69225876T2 - Cachesteuerungsschaltung - Google Patents

Cachesteuerungsschaltung

Info

Publication number
DE69225876T2
DE69225876T2 DE69225876T DE69225876T DE69225876T2 DE 69225876 T2 DE69225876 T2 DE 69225876T2 DE 69225876 T DE69225876 T DE 69225876T DE 69225876 T DE69225876 T DE 69225876T DE 69225876 T2 DE69225876 T2 DE 69225876T2
Authority
DE
Germany
Prior art keywords
control circuit
cache control
cache
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69225876T
Other languages
English (en)
Other versions
DE69225876D1 (de
Inventor
Bradford B Beavers
Paul A Reed
Jeff A Slaton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69225876D1 publication Critical patent/DE69225876D1/de
Publication of DE69225876T2 publication Critical patent/DE69225876T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69225876T 1991-12-24 1992-12-14 Cachesteuerungsschaltung Expired - Fee Related DE69225876T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81307891A 1991-12-24 1991-12-24

Publications (2)

Publication Number Publication Date
DE69225876D1 DE69225876D1 (de) 1998-07-16
DE69225876T2 true DE69225876T2 (de) 1998-12-10

Family

ID=25211397

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225876T Expired - Fee Related DE69225876T2 (de) 1991-12-24 1992-12-14 Cachesteuerungsschaltung

Country Status (3)

Country Link
EP (1) EP0549219B1 (de)
JP (1) JPH05257809A (de)
DE (1) DE69225876T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
WO1996033462A1 (de) * 1995-04-18 1996-10-24 International Business Machines Corporation Cache-speicher
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
WO2007094046A1 (ja) 2006-02-14 2007-08-23 Fujitsu Limited コヒーレンシ維持装置およびコヒーレンシ維持方法
JP5440067B2 (ja) * 2009-09-18 2014-03-12 富士通株式会社 キャッシュメモリ制御装置およびキャッシュメモリ制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
ATE170642T1 (de) * 1990-06-15 1998-09-15 Compaq Computer Corp Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien

Also Published As

Publication number Publication date
DE69225876D1 (de) 1998-07-16
JPH05257809A (ja) 1993-10-08
EP0549219A1 (de) 1993-06-30
EP0549219B1 (de) 1998-06-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee