DE69208132D1 - Cache-Speichersteuerungsanordnung - Google Patents

Cache-Speichersteuerungsanordnung

Info

Publication number
DE69208132D1
DE69208132D1 DE69208132T DE69208132T DE69208132D1 DE 69208132 D1 DE69208132 D1 DE 69208132D1 DE 69208132 T DE69208132 T DE 69208132T DE 69208132 T DE69208132 T DE 69208132T DE 69208132 D1 DE69208132 D1 DE 69208132D1
Authority
DE
Germany
Prior art keywords
control arrangement
cache control
cache
arrangement
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69208132T
Other languages
English (en)
Inventor
Jamshed Hormazdyar Mirza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69208132D1 publication Critical patent/DE69208132D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
DE69208132T 1991-04-15 1992-04-01 Cache-Speichersteuerungsanordnung Expired - Lifetime DE69208132D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/685,583 US5625793A (en) 1991-04-15 1991-04-15 Automatic cache bypass for instructions exhibiting poor cache hit ratio

Publications (1)

Publication Number Publication Date
DE69208132D1 true DE69208132D1 (de) 1996-03-21

Family

ID=24752832

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69208132T Expired - Lifetime DE69208132D1 (de) 1991-04-15 1992-04-01 Cache-Speichersteuerungsanordnung

Country Status (4)

Country Link
US (1) US5625793A (de)
EP (1) EP0509676B1 (de)
JP (1) JPH04324546A (de)
DE (1) DE69208132D1 (de)

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US9020900B2 (en) 2010-12-14 2015-04-28 Commvault Systems, Inc. Distributed deduplicated storage system
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Also Published As

Publication number Publication date
JPH04324546A (ja) 1992-11-13
US5625793A (en) 1997-04-29
EP0509676A1 (de) 1992-10-21
EP0509676B1 (de) 1996-02-07

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Legal Events

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8332 No legal effect for de