DE69015854T2 - Anordnung von Halbleiterbauelementen und Verfahren und Vorrichtung zur Montage von Halbleiterbauelementen. - Google Patents

Anordnung von Halbleiterbauelementen und Verfahren und Vorrichtung zur Montage von Halbleiterbauelementen.

Info

Publication number
DE69015854T2
DE69015854T2 DE69015854T DE69015854T DE69015854T2 DE 69015854 T2 DE69015854 T2 DE 69015854T2 DE 69015854 T DE69015854 T DE 69015854T DE 69015854 T DE69015854 T DE 69015854T DE 69015854 T2 DE69015854 T2 DE 69015854T2
Authority
DE
Germany
Prior art keywords
semiconductor components
arrangement
assembling
assembling semiconductor
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69015854T
Other languages
English (en)
Other versions
DE69015854D1 (de
Inventor
Eiichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of DE69015854D1 publication Critical patent/DE69015854D1/de
Publication of DE69015854T2 publication Critical patent/DE69015854T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
DE69015854T 1989-03-20 1990-03-02 Anordnung von Halbleiterbauelementen und Verfahren und Vorrichtung zur Montage von Halbleiterbauelementen. Expired - Lifetime DE69015854T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6587989 1989-03-20
JP1303152A JP2855719B2 (ja) 1989-03-20 1989-11-24 半導体装置

Publications (2)

Publication Number Publication Date
DE69015854D1 DE69015854D1 (de) 1995-02-23
DE69015854T2 true DE69015854T2 (de) 1995-06-14

Family

ID=26407039

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015854T Expired - Lifetime DE69015854T2 (de) 1989-03-20 1990-03-02 Anordnung von Halbleiterbauelementen und Verfahren und Vorrichtung zur Montage von Halbleiterbauelementen.

Country Status (4)

Country Link
US (1) US5101324A (de)
EP (1) EP0389826B1 (de)
JP (1) JP2855719B2 (de)
DE (1) DE69015854T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04179263A (ja) * 1990-11-14 1992-06-25 Hitachi Ltd 樹脂封止型半導体装置とその製造方法
KR940003560B1 (ko) * 1991-05-11 1994-04-23 금성일렉트론 주식회사 적층형 반도체 패키지 및 그 제조방법.
DE4129146A1 (de) * 1991-09-02 1993-03-04 Siemens Nixdorf Inf Syst Bandfoermiger hilfstraeger als montagehilfe fuer die zeilenweise montage von halbleiterchips auf einer passflaeche eines traegerelementes und ein zugehoeriges montageverfahren
JP2721093B2 (ja) * 1992-07-21 1998-03-04 三菱電機株式会社 半導体装置
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US6205654B1 (en) * 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US5294827A (en) * 1992-12-14 1994-03-15 Motorola, Inc. Semiconductor device having thin package body and method for making the same
US5604376A (en) * 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
KR0147259B1 (ko) * 1994-10-27 1998-08-01 김광호 적층형 패키지 및 그 제조방법
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
KR100192180B1 (ko) * 1996-03-06 1999-06-15 김영환 멀티-레이어 버텀 리드 패키지
US5700723A (en) * 1996-05-15 1997-12-23 Lsi Logic Corporation Method of packaging an integrated circuit
US6166894A (en) * 1999-03-15 2000-12-26 Lucent Technologies Inc. PCB based protector cartridge
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6608763B1 (en) 2000-09-15 2003-08-19 Staktek Group L.P. Stacking system and method
US6462408B1 (en) * 2001-03-27 2002-10-08 Staktek Group, L.P. Contact member stacking system and method
JP5093244B2 (ja) 2007-11-01 2012-12-12 パナソニック株式会社 電子部品実装構造体およびその製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3395318A (en) * 1967-02-13 1968-07-30 Gen Precision Inc Circuit board card arrangement for the interconnection of electronic components
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
JPS54144872A (en) * 1978-05-04 1979-11-12 Omron Tateisi Electronics Co Electronic circuit device
JPS5662351A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory
JPS56167357A (en) * 1980-05-27 1981-12-23 Sharp Corp Tape carrier substrate for semiconductor device
US4423468A (en) * 1980-10-01 1983-12-27 Motorola, Inc. Dual electronic component assembly
US4410905A (en) * 1981-08-14 1983-10-18 Amp Incorporated Power, ground and decoupling structure for chip carriers
FR2512990B1 (fr) * 1981-09-11 1987-06-19 Radiotechnique Compelec Procede pour fabriquer une carte de paiement electronique, et carte realisee selon ce procede
JPS5920645U (ja) * 1982-07-30 1984-02-08 富士通株式会社 集合半導体モジユ−ル
GB2137805B (en) * 1982-11-19 1987-01-28 Stanley Bracey Chip carrier
JPS6157542U (de) * 1984-09-18 1986-04-17
US4783697A (en) * 1985-01-07 1988-11-08 Motorola, Inc. Leadless chip carrier for RF power transistors or the like
JPS61183570U (de) * 1985-05-09 1986-11-15
JPS61199051U (de) * 1985-05-31 1986-12-12
DE3533993A1 (de) * 1985-09-24 1987-04-02 Borg Instr Gmbh Verfahren zum kontaktieren auf leiterbahnen, vorrichtung zum ausueben des verfahrens und fluessigkristallzelle mit aufgebondeten chip
JPH0810746B2 (ja) * 1987-02-19 1996-01-31 日本電気株式会社 メモリーモジュール
US4933810A (en) * 1987-04-30 1990-06-12 Honeywell Inc. Integrated circuit interconnector
JP2603636B2 (ja) * 1987-06-24 1997-04-23 株式会社日立製作所 半導体装置
JPH0193196A (ja) * 1987-10-02 1989-04-12 Nec Corp プリント回路基板
JP2559461B2 (ja) * 1988-05-23 1996-12-04 株式会社日立製作所 半導体装置の製造方法
JPH02174240A (ja) * 1988-12-27 1990-07-05 Hitachi Maxell Ltd 半導体装置の製造方法
JPH02290048A (ja) * 1989-02-15 1990-11-29 Matsushita Electric Ind Co Ltd 積層型半導体の実装方法

Also Published As

Publication number Publication date
US5101324A (en) 1992-03-31
JPH0320051A (ja) 1991-01-29
JP2855719B2 (ja) 1999-02-10
EP0389826A1 (de) 1990-10-03
EP0389826B1 (de) 1995-01-11
DE69015854D1 (de) 1995-02-23

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Legal Events

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Free format text: HOFFMANN, E., DIPL.-ING., PAT.-ANW., 82166 GRAEFELFING

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