DE69011133D1 - Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern. - Google Patents
Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern.Info
- Publication number
- DE69011133D1 DE69011133D1 DE69011133T DE69011133T DE69011133D1 DE 69011133 D1 DE69011133 D1 DE 69011133D1 DE 69011133 T DE69011133 T DE 69011133T DE 69011133 T DE69011133 T DE 69011133T DE 69011133 D1 DE69011133 D1 DE 69011133D1
- Authority
- DE
- Germany
- Prior art keywords
- bit
- multiplexor
- random
- output
- weighting factor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2101/00—Indexing scheme relating to the type of digital function generated
- G06F2101/14—Probability distribution functions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/398,772 US5043988A (en) | 1989-08-25 | 1989-08-25 | Method and apparatus for high precision weighted random pattern generation |
PCT/US1990/004832 WO1991003014A2 (en) | 1989-08-25 | 1990-08-24 | Method and apparatus for high precision weighted random pattern generation |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69011133D1 true DE69011133D1 (de) | 1994-09-01 |
DE69011133T2 DE69011133T2 (de) | 1995-01-26 |
Family
ID=23576759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69011133T Expired - Fee Related DE69011133T2 (de) | 1989-08-25 | 1990-08-24 | Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5043988A (de) |
EP (1) | EP0541537B1 (de) |
JP (1) | JP3037408B2 (de) |
AT (1) | ATE109289T1 (de) |
CA (1) | CA2065341C (de) |
DE (1) | DE69011133T2 (de) |
WO (1) | WO1991003014A2 (de) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2814268B2 (ja) * | 1989-07-21 | 1998-10-22 | 安藤電気株式会社 | 演算機能内蔵メモリ用パターン発生装置 |
DE69126199T2 (de) * | 1991-02-21 | 1997-10-16 | Ibm | Integrierter Schaltkreis mit eingebautem Selbsttest für die Erkennung logischer Fehler |
JP2584172B2 (ja) * | 1991-08-23 | 1997-02-19 | インターナショナル・ビジネス・マシーンズ・コーポレイション | デイジタル試験信号発生回路 |
US5323400A (en) * | 1991-09-09 | 1994-06-21 | Northern Telecom Limited | Scan cell for weighted random pattern generation and method for its operation |
US5369648A (en) * | 1991-11-08 | 1994-11-29 | Ncr Corporation | Built-in self-test circuit |
US5394405A (en) * | 1992-04-24 | 1995-02-28 | International Business Machines Corporation | Universal weight generator |
US5297151A (en) * | 1992-06-17 | 1994-03-22 | International Business Machines Corporation | Adjustable weighted random test pattern generator for logic circuits |
JPH063424A (ja) * | 1992-06-22 | 1994-01-11 | Mitsubishi Electric Corp | 集積回路装置、および集積回路装置に組込まれるテストデータ発生回路 |
ES2070719B1 (es) * | 1993-03-17 | 1997-10-16 | Consejo Superior Investigacion | Estructura no lineal para la generacion de secuencias pseudoaleatorias. |
US5414716A (en) * | 1993-09-22 | 1995-05-09 | Mitsubishi Electronic Research Laboratories, Inc. | Weighting system for testing of circuits utilizing determination of undetected faults |
US5598154A (en) * | 1994-12-02 | 1997-01-28 | Unisys Corporation | Apparatus and method for generating and utilizing pseudonoise code sequences |
US5982194A (en) * | 1995-12-28 | 1999-11-09 | Lsi Logic Corporation | Arithmetic and logic function circuits optimized for datapath layout |
US5968194A (en) * | 1997-03-31 | 1999-10-19 | Intel Corporation | Method for application of weighted random patterns to partial scan designs |
US5983380A (en) * | 1997-09-16 | 1999-11-09 | International Business Machines Corporation | Weighted random pattern built-in self-test |
US6272653B1 (en) | 1997-11-14 | 2001-08-07 | Intrinsity, Inc. | Method and apparatus for built-in self-test of logic circuitry |
US6429795B1 (en) | 1997-12-08 | 2002-08-06 | Intrinsity, Inc. | Method and apparatus for transforming pseudorandom binary patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs |
US6295622B1 (en) | 1997-12-08 | 2001-09-25 | Intrinsity, Inc. | Method and apparatus for transforming pseudorandom binary test patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs |
US6662327B1 (en) | 1998-05-13 | 2003-12-09 | Janusz Rajski | Method for clustered test pattern generation |
JP3825179B2 (ja) * | 1998-07-17 | 2006-09-20 | 富士通株式会社 | 相関器 |
US6573703B1 (en) * | 1999-04-05 | 2003-06-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6658616B1 (en) * | 1999-11-22 | 2003-12-02 | Cadence Design Systems, Inc. | Method for improving the efficiency of weighted random pattern tests through reverse weight simulation using effective pattern masks |
US6985918B2 (en) * | 2001-10-17 | 2006-01-10 | Hewlett-Packard Development Company, L.P. | Random number generators implemented with cellular array |
US6910057B2 (en) * | 2001-10-17 | 2005-06-21 | Hewlett-Packard Development Company, L.P. | Truth table candidate reduction for cellular automata based random number generators |
US7571200B2 (en) * | 2002-04-24 | 2009-08-04 | Hewlett-Packard Development Company, L.P. | Seedable pseudo-random number generator |
US7080298B2 (en) * | 2003-02-04 | 2006-07-18 | Toshiba America Electronic Components | Circuit apparatus and method for testing integrated circuits using weighted pseudo-random test patterns |
KR100622128B1 (ko) * | 2004-12-17 | 2006-09-19 | 한국전자통신연구원 | 병렬 처리 축소 키 생성기 |
US20110191129A1 (en) * | 2010-02-04 | 2011-08-04 | Netzer Moriya | Random Number Generator Generating Random Numbers According to an Arbitrary Probability Density Function |
WO2012124118A1 (ja) * | 2011-03-17 | 2012-09-20 | 富士通株式会社 | メモリ試験支援方法及びメモリ試験支援装置 |
GB201711055D0 (en) * | 2017-07-10 | 2017-08-23 | Accelercomm Ltd | Electronic device with bit pattern generation, integrated circuit and method for polar coding |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3633100A (en) * | 1970-05-12 | 1972-01-04 | Ibm | Testing of nonlinear circuits by comparison with a reference simulation with means to eliminate errors caused by critical race conditions |
US3636443A (en) * | 1970-10-29 | 1972-01-18 | Ibm | Method of testing devices using untested devices as a reference standard |
US3719885A (en) * | 1971-12-13 | 1973-03-06 | Ibm | Statistical logic test system having a weighted random test pattern generator |
JPS59160236A (ja) * | 1983-03-01 | 1984-09-10 | Matsushita Electric Ind Co Ltd | 擬似乱数発生装置 |
US4546473A (en) * | 1983-05-06 | 1985-10-08 | International Business Machines Corporation | Random pattern self test design |
FR2553540B1 (fr) * | 1983-10-13 | 1986-01-03 | Centre Nat Rech Scient | Dispositif de test aleatoire pour circuits logiques, notamment microprocesseurs |
US4745355A (en) * | 1985-06-24 | 1988-05-17 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4687988A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4801870A (en) * | 1985-06-24 | 1989-01-31 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4688223A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4754215A (en) * | 1985-11-06 | 1988-06-28 | Nec Corporation | Self-diagnosable integrated circuit device capable of testing sequential circuit elements |
IT1186523B (it) * | 1985-12-31 | 1987-11-26 | Sgs Microelettronica Spa | Procedimento per la valutazione dei parametri di processo nella fabbricazione di dispositivi a semiconduttore |
JPH0746127B2 (ja) * | 1986-05-20 | 1995-05-17 | 三菱電機株式会社 | 半導体試験装置 |
US4817093A (en) * | 1987-06-18 | 1989-03-28 | International Business Machines Corporation | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure |
-
1989
- 1989-08-25 US US07/398,772 patent/US5043988A/en not_active Expired - Lifetime
-
1990
- 1990-08-24 WO PCT/US1990/004832 patent/WO1991003014A2/en active IP Right Grant
- 1990-08-24 AT AT90913270T patent/ATE109289T1/de active
- 1990-08-24 DE DE69011133T patent/DE69011133T2/de not_active Expired - Fee Related
- 1990-08-24 JP JP51253890A patent/JP3037408B2/ja not_active Expired - Fee Related
- 1990-08-24 CA CA 2065341 patent/CA2065341C/en not_active Expired - Fee Related
- 1990-08-24 EP EP19900913270 patent/EP0541537B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69011133T2 (de) | 1995-01-26 |
ATE109289T1 (de) | 1994-08-15 |
WO1991003014A3 (en) | 1991-04-04 |
CA2065341C (en) | 1998-05-26 |
JPH04507470A (ja) | 1992-12-24 |
EP0541537B1 (de) | 1994-07-27 |
US5043988A (en) | 1991-08-27 |
EP0541537A1 (de) | 1993-05-19 |
JP3037408B2 (ja) | 2000-04-24 |
WO1991003014A2 (en) | 1991-03-07 |
CA2065341A1 (en) | 1991-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |