EP0541537B1 - Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern - Google Patents

Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern Download PDF

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EP0541537B1
EP0541537B1 EP19900913270 EP90913270A EP0541537B1 EP 0541537 B1 EP0541537 B1 EP 0541537B1 EP 19900913270 EP19900913270 EP 19900913270 EP 90913270 A EP90913270 A EP 90913270A EP 0541537 B1 EP0541537 B1 EP 0541537B1
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Prior art keywords
bit
random
multibit
weighted
random pattern
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French (fr)
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EP0541537A1 (de
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Franc Brglez
Gershon Kedem
Clay Samuel Gloster, Jr.
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Nortel Networks Ltd
Nortel Networks Corp
MCNC
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Northern Telecom Ltd
Nortel Networks Corp
MCNC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2101/00—Indexing scheme relating to the type of digital function generated
    • G06F2101/14—Probability distribution functions

Definitions

  • This invention relates to random pattern generation systems and more particularly to a method and apparatus for efficiently generating weighted random patterns having a high degree of precision.
  • test patterns For example, a 10 input "AND" gate can be tested in as few as 11 test patterns.
  • generation of test patterns with an algorithm, given a circuit structure, is often considered a more difficult task than generating randomly generated test patterns for their fault coverage.
  • the weighted random pattern generator of the IBM patents is comprised of a random pattern generator of the linear feedback shift register configuration, a weighting circuit having a plurality of cascaded "AND” gates, and a multiplexor.
  • the first five bits of the shift register are the only random bits used and are connected to the cascaded "AND” gates.
  • the first bit is connected directly to the multiplexor as well as one input of the first "AND” gate.
  • Each successive random bit of the five are input to a successive one of the "AND” gates.
  • the second input to the second, third and fourth "AND" gates are the outputs of the preceding gate. In addition to being inputs for successive "AND" gates of the weighting circuit, these outputs are also inputs to the multiplexor.
  • the series of gates causes the probability of producing a binary ONE at each successive output to be one half that of producing a binary ONE at the preceding output.
  • the probabilities are one-half, one-fourth, one-eighth, one sixteenth, and one-thirty-second.
  • obtaining a low probability (one very close to zero) or a high probability (one very close to one) is very time consuming since k clock cycles are required to obtain a signal, i.e. output, with probability of 1/2 k or 1-1/2 k .
  • each input to a circuit to be tested requires one weighted pattern generator. This results in a great deal of hardware overhead. Although increased precision could be obtained using this system, the hardware complexity would continue to increase.
  • U.S. patent number 3,719,885 to Carpenter et al. entitled "Statistical Logic Test System Having A Weighted Random Test Pattern Generator” also describes a weighted random pattern generation system having a decoder which converts random patterns from binary to decimal producing a large number of weight variations in order to achieve a high fault coverage. This results in the number of test patterns being proportional to the circuit switching activity, i.e. the complexities of the hidden circuit logic.
  • the Carpenter et al. weight pattern generator consists of a random pattern generator, a bit decoder and a weighting circuit.
  • the bit decoder operates as a binary to decimal decoder producing a large number of outputs.
  • the weighting circuit provides a larger number of bits to those elements of circuit under test which require a greater number of test patterns to insure the functional integrity of that particular element. In essence, the weighting performed in Carpenter et al. simply provides a means for supplying certain circuit element inputs with a larger number of test bits than other inputs.
  • the weighting combines outputs of the decoder based on the resistance a given element, i.e. circuit input, has to random pattern testing.
  • test patterns In order to ensure the functional integrity of a highly complex circuit using the Carpenter et al. system, it is necessary to generate an extremely large number of test patterns. Moreover, testing time will increase with the complexity of the circuit. Finally, it is not possible to modify the test patterns so as to achieve a certain probability of producing a given test pattern, to thereby decrease the number of test patterns necessary to insure the functionality of the circuit under test.
  • a system for obtaining test patterns having certain probabilities is also described by David et al. in U.S. patent number 4,730,319 entitled "Device For Transforming The Occurrence Probability Of Logic Vectors And For The Generation Of Vector Sequences With Time Variable Probabilities.” David et al. provides a scheme whereby the probability that a given test pattern must occur is determined. Each pattern is then loaded into memory a number of times proportional to the total number of memory locations based upon the probability the test pattern must occur. A random number generator, which inherently has an equal chance of producing any given result, generates the address of the memory location where the test pattern is stored. The probability of obtaining a given test pattern is dependent upon the number of times that the pattern has been loaded into memory. The probability of selecting a particular memory location is not affected.
  • David et al. permits probabilities to be allocated, this allocation is based upon a manual load of patterns into memory based upon desired probability of occurrence. The probability of selecting one test pattern over another is constant in that the probability of selecting each memory location is equal. The selecting technique does not permit any modification of the random pattern. Moreover, the David et al. testing scheme is inefficient because the test vectors are not generated by modifying a random pattern but rather are manually determined and then forced into selection using the probability. Due to the high labor intensity needed to accomplish this task, testing of complex circuits will be very time consuming.
  • JP-A 59 160 236 (Matsushita Denki Sangyo K.K.) 10-09-1984, reproduced in Patent Abstracts of Japan, Vol. 9, No. 13 (P-328) (1736) January 19, 1985, describes a pseudo random number generating device consisting of a binary counter 1 which continuously provides a periodic count.
  • a code generating circuit 4 generates a weighting changing code with one weighting changing code being generated for each period of a counter.
  • a multiplexor 3 outputs a pseudo random number.
  • weighted random pattern generators for producing weighted test patterns or vectors
  • these weighted random pattern generators may require a large number of test vectors in order to obtain high fault coverage.
  • the precision of prior art weighted random number generators is limited, so that any arbitrary probability cannot be readily generated.
  • Prior art weighted random number generators employ complex hardware which, by definition, limits the speed of weighted random number generation. Modification of the random patterns is also difficult.
  • an apparatus for generating weighted random patterns including a circular or recirculating memory which contains a plurality of multibit weighting factors.
  • a random pattern generator for example in the form of a known linear feedback shift register or a cellular automata register, generates random patterns of multiple bits.
  • a circuit is provided for combining the multibit weighting factors stored in the memory with a random pattern generated by the random pattern generator to obtain a weighted random test pattern.
  • a weighted random pattern generation system having a memory with a plurality of multibit weighting factors stored therein, a random pattern generator for generating a plurality of multibit random bit patterns, and means, connected to said memory and said random pattern generator, for combining said multibit weighting factors stored in said memory with said multibit random bit patterns, which system is characterized by: said memory being a circular memory having a plurality of multibit weighting factors stored therein; and said combining means being connected to said circular memory and said random pattern generator, for combining said multibit weighting factors stored in said circular memory with said multibit random bit patterns to form a multibit weighted random pattern.
  • a corresponding weighted random pattern generation method is defined in claim 21.
  • each multibit weighting factor represents the probability that a single bit of the weighted random pattern will have a binary value of ONE. As the need for precision of this probability increases, the number of bits in the multibit weighting factor also increases. Thus any desired precision may be obtained.
  • the multibit weighting factor for that bit is combined, on a bit by bit basis, with bits from a random number generator, using the combining circuit of the present invention. This combining takes place in a single clock cycle.
  • the next multibit weighting factor stored in memory is combined, on a bit by bit basis, with selected bits for the random number generator, using the combining circuit of the present invention. The process continues through all locations of the circular memory and restarts through the memory in a circular fashion.
  • the combining circuit of the present invention is a plurality of serially connected multiplexor gates. Each gate has two data inputs; ie., one bit from the multibit weighting factor stored in circular memory and the output bit of the previous gate. The selected bits from the random pattern generator control the multiplexor gates thus determining whether the output of a given multiplexor gate is the weight bit or the output from the preceding multiplexor gate.
  • A is the selected bit of a subtotal of r bits of the random pattern
  • W is the selected bit of a weighting factor associated with Z j having a total of r+1 bits
  • Z j is the weighted random bit which forms one bit of the weighted random pattern.
  • This boolean function may be implemented using simple multiplexor hardware thus decreasing the generation time and circuit complexity.
  • the boolean function produces one bit of the weighted random number in a single clock cycle.
  • any probability is obtainable, with any desired degree of precision, fewer test patterns will need to be generated while simultaneously providing increased fault coverage.
  • virtually any probability of generating a given bit of a test pattern having a binary value of ONE can be achieved utilizing simple hardware resulting in a high precision weighted random pattern generator which provides increased fault coverage while generating a decreased number of test patterns.
  • Figure 1 is a high-level block diagram of a generic testing system including a high precision weighted random pattern generation system according to the present invention.
  • a generic testing system 1 contains a controller 2 , a device under test 3 , an analyzer 4 , a comparator 5 , a memory 6 , a pass/fail register 7 , and a weighted random pattern generation system 8 .
  • the device under test (DUT) 3 receives test patterns, also known as test vectors, from a weighted random pattern generation system 8 .
  • the output of DUT 3 resulting from the DUT's operation on the test pattern is transmitted to the analyzer 4 .
  • the results of the test is compared by a comparator 5 with a known set of values stored in memory 6 .
  • the pass/fail register is set to pass or fail depending on whether the comparator concludes that the DUT passed or failed the test. All operations are controlled by the controller 2 .
  • this arrangement for example, can be built into a single integrated circuit, imbedded in a board-level system as part of a self-test scheme, or made an integral part of a general purpose testing system.
  • the present invention will generate a given bit of a test pattern within any desired probability.
  • the weighted random pattern generation system 8 of the present invention can achieve any probability of generating a bit of a test pattern having a binary value of ONE. This results in high precision and ensures complete and accurate testing of a complex circuit while generating a minimal number of test patterns.
  • the weighted random pattern generation system 8 is comprised of three major components, those being a circular memory 11 , a random pattern generator 12 and a combining means 13 . Both the circular memory 11 and the random pattern generator 12 are connected to and provide inputs to the combining means 13 .
  • a register 14 stores the test bits produced by the combining means.
  • the weighted random pattern generation system 8 produces one weighted bit of the weighted test pattern during each clock cycle. Each weighted bit produced is shifted into the weighted random pattern register 14 in which the test bits are accumulated into a test pattern, also referred to as a "test vector". Since, generally speaking, the width of the test pattern, i.e. the number of bits, is unlimited, the size of register 14 varies according to the width of the test pattern.
  • a number of bits r where r is the desired precision for the bit to be generated, Z , are selected from the source register during processing as control inputs to the combining means 13 .
  • the bit locations within the source register 15 from which the bits are selected can be arbitrary in principle. However, for best results, the bits should be truly independent. This is achieved in most cases by maximizing the spacing between the selected r bits.
  • a new clock cycle then starts, resulting in tapping r bits from the random source register 15 and in selecting the next weighting factor of length r or r+1 which as a result of circulation in memory 11 is located at address zero.
  • the weighting factor Q j+1 is then stored in the weight register 16 and inputs to the combining means from the random source register 15 and the weight register 16 are then processed to generate the next significant bit Z j+1 of the weighted pattern register. This process continues until a number of weighted bits equal to the length, b, of the weighted test pattern have been generated.
  • weighted test pattern Once the weighted test pattern has been generated, a new test pattern can be produced.
  • the same weighting factors are used for each test pattern produced for a particular circuit under test.
  • bits from the pattern source register are pseudo-random and hence different in general for each test pattern produced for a given circuit under test as well as for each weighted bit with a weighted test pattern.
  • the scrambling means 17 may take a variety of permutations in conjunction with a series of parallel EXCLUSIVE-OR gates.
  • the combining means 13 is comprised of a set of cascading multiplexor gates M 0... M r-1 each having three inputs X 0... X r-1 , W 0... W r-1 , A 0... A r-1 and one output Y 1... Y r .
  • the output Y i from one gate is connected to one of the three inputs X i of the immediately succeeding multiplexor gate.
  • the other two inputs W i and A i respectively are bits from the weighting factor stored in the weight register 16 and from the random source register 15 .
  • the weight bit W i from the weight register and X i tied to the output Y i from the immediately preceding multiplexor gate M i-1 , are the two data inputs to the multiplexor gate M i .
  • the bit from the random source register A i acts as a control bit for the multiplexor gate M i .
  • the output Y i+1 of multiplexor M i will be either the value of input X i or input W i depending upon whether control input A i is binary ZERO or ONE.
  • the one exception to this general structure is the first multiplexor gate M 0 in the cascading series in which the two data inputs X 0 and W 0 are the two bits W r and W 0 of the weighting factor Q j , i.e. ( W 0,... W r-1 , W r ), stored in the weight register 16 and the control bit A 0 is the bit from the random source register 15 .
  • the precision r is the desired precision for the test pattern. For illustration purposes, assume that the weighting factor Q j , associated with the weighted test bit Z j , has been loaded into weight register 16 .
  • a 0 will be binary ZERO half the time and binary ONE the other half of the time, since A 0 is driven by a register cell from an unbiased pseudo random source 12 .
  • W r weight bit has no effect on Y 1 and therefore is simply not considered for purposes of illustration. This is true regardless of the desired precision.
  • an alternative embodiment for the combining means 13 can be used wherein input X 0 to multiplexor M 0 is tied to binary ZERO rather than W r .
  • a precision of 2 requires use of two multiplexors, M 0 and M 1, in the combining means 13 .
  • the combining means now has two control inputs A 0 and A 1 respectively for multiplexors M 0 and M 1.
  • a 1 will be ZERO half the time and ONE the other half of the time since A 1 is driven by a register cell from an unbiased pseudo random source 12 .
  • Equation 1 represents the probability of attaining the value 1 for output Y 1
  • weighting bits W 2 and W 0 are inputs to multiplexor M 0 and weighting bit W 1 is an input to multiplexor M 1.
  • the set of signal probabilities ⁇ 0,1/4,2/4,3/4,1 ⁇ can be generated by the output Y 2 of the second multiplexor M 2 using the weighting bits from Table 1.
  • the present invention permits uniformly decreasing the spacing between obtainable output probabilities by simply increasing the number of multiplexors and the corresponding data and control inputs, i.e. increasing the precision r.
  • the combining means 13 is comprised of a cascading series of three multiplexors M 0, M 1 and M 2.
  • the control inputs selected from random source register 15 are A 0, A 1 and A 2 for multiplexors M 0, M 1 and M 2.
  • a 2 will be binary ZERO one half the time and binary ONE the other half of the time since A 2 is driven by a register cell from an unbiased pseudo random source 12 .
  • a 2 will select the input X 2 as output Y 3 one half of the time and the input W 2 as output Y 3 the other half of the time.
  • the spacing between obtainable probabilities can be uniformly decreased by increasing the number of multiplexors and the corresponding input signals, i.e. increasing the precision r.
  • the order of the weighting bits represented as W 0, W 1, ... W r-1 , W r correspond with ordinary binary encoding for signals in that W 0 represents the least significant bit and W r represents the most significant bit.
  • the weighting factor Q (0011) assigns a signal probability of 3/8 to the multiplexor output.
  • precision r As the value of the precision r, is increased, more signal probabilities which are not attainable using the disclosures of the IBM patents can be achieved through the present invention. In general, the choice for precision r will depend upon the properties of the DUT 3 . As the value of r increases, the number of weighted random patterns required to test the circuit will generally decrease.
  • the combining means 13 is comprised of r cascading multiplexor gates M 0.. M r-1 , wherein r is the desired resolution.
  • the combining means 13 combines r bits A 0... A r-1 from random pattern source register 15 and r+1 weighting bits W 0... W r from memory 11 via the weight register 16 .
  • a r-1 represents the r bits from the random pattern source 15 ; W r represents the r th bit of the weighting factor Q which is connected to input X 0 of the multiplexor gate of M 0; W 0...
  • W r-1 represent the remaining r bits of the weighting factor which are connected to inputs W 0... W r-1 of the multiplexor gates M ; Y 1 represents the output from multiplexor gate M 0; and Y 2... Y r represent the remaining outputs for the remaining multiplexor gates M 1... M r-1 ; and Z j represents the output Y r of multiplexor M r-1 .
  • the output of the final multiplexor gate M r-1 is the weighted random bit Y r , and is shifted as a bit Z j into the jth position of the weighted random pattern register 14 .
  • the conditions under which the combining means 13 will generate weighted random patterns with a specified probability can also be represented to the rth iteration by a mathematical formula.
  • the joint probability that random bit A i has a binary value of 1 and random bit A j has a binary value of 1 is equal to the probability that random bit A i has a binary value of 1 multiplied by the probability that random bit A j has a binary value of 1.

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Claims (29)

  1. System (8) zum Erzeugen eines gewichteten Zufallsmusters, mit einem Speicher, in dem eine Vielzahl von Multibit-Gewichtungsfaktoren (Q) gespeichert ist, einem Zufallsmustergenerator (12) zum Erzeugen einer Vielzahl von Multibit-Zufalls-Bitmustern, und einer Einrichtung (13), die mit dem genannten Speicher und dem genannten Zufallsmustergenerator verbunden ist, um die genannten Multibit-Gewichtungsfaktoren, die in dem genannten Speicher gespeichert sind, mit den genannten Multibit-Zufalls-Bitmustern zu kombinieren,
    gekennzeichnet durch:
       der genannte Speicher ist ein Ringspeicher (11); und
       die genannte Kombinationseinrichtung (13) führt die genannte Kombination der genannten Multibit-Gewichtungsfaktoren zur Bildung eines gewichteten Multibit-Zufallsmusters nach Art einer Bitfolge durch.
  2. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die genannte Kombinationseinrichtung die folgenden Merkmale aufweist:
       eine Anzahl in Reihe angeschlossener Stufen (M), von denen jede eine Vielzahl von Eingängen (A, X, W) und einen Ausgang (Y) aufweist, wobei der Ausgang einer unmittelbar vorangehenden Stufe mit einem (X) der Vielzahl von Eingängen einer unmittelbar nachfolgenden Stufe verbunden ist;
       ein jeweiliges Bit der genannten Multibit-Gewichtungsfaktoren (W) und ein jeweiliges Bit der genannten Zufalls-Bitmuster (A) werden an die Eingänge einer jeweiligen der genannten Stufen angeschlossen.
  3. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 2:
       worin eine der genannten Vielzahl von Eingängen einer jeden der genannten Stufen einen Steuereingang (A) aufweist; und
       worin das genannte jeweilige Bit des genannten Zufalls-Bitmusters mit einem jeweiligen der genannten Steuereingänge verbunden ist.
  4. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die genannte Kombinationseinrichtung eine Vielzahl von in Reihe angeschlossener multiplexer Gatter (M) aufweist, jedes der genannten, in Reihe angeschlossener multiplexer Gatter einen ersten und zweiten Dateneingang (X, W), einen Steuereingang (A) und einen Ausgang (Y) aufweist, wobei der binäre Wert des genannten Ausganges (Y) einer des binären Werts des genannten ersten und des genannten zweiten Dateneingangs (X, W) in Abhängigkeit vom binären Wert des genannten Steuereingangs ist; der Ausgang (Y) einer unmittelbar vorangehenden Stufe mit dem ersten Dateneingang (X) einer unmittelbar nachfolgenden Stufe verbunden ist; ein jeweiliges Bit der genannten Multibit-Gewichtungsfaktoren an jeweils einen der genannten zweiten Dateneingänge (W) angeschlossen ist; und ein jeweiliges Bit des genannten Zufalls-Bitmusters mit einem jeweiligen der genannten Steuereingänge (A) verbunden ist.
  5. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die genannte Kombinationseinrichtung (13) die genannten Multibit-Gewichtungsfaktoren und das genannte Zufalls-Bitmuster entsprechend der folgenden Boole'schen Funktion kombiniert:

    Y⁰ = W r ;
    Figure imgb0050
    Y i = A ¯ i-1 Y i-1 + A i-1 W i-1 ,i=1...r;
    Figure imgb0051

    wobei r die gewünschte Genauigkeit ist, Ai ein Bit des genannten Zufallsmustes ist, Wi ein Bit des ausgewählten der genannten Gewichtungsfaktoren ist, Yi das Ergebnis der Kombination von Ai und Wi ist, ausgenommen Y⁰, das eingesetzt wird für Wr, und Yr das Ergebnis der abschließenden Interation zum Erzeugen eines Bits des genannten gewichteten Zufallsmusters ist.
  6. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die genannte Kombinationseinrichtung (13) die genannten Multibit-Gewichtungsfaktoren und die genannten Zufalls-Bitmuster entsprechend der folgenden Boole'schen Funktion kombiniert:

    Z j = A ¯ r-1 A ¯ r-2 .... A ¯ ⁰W r + A r-1 W r-1 +
    Figure imgb0052
    A ¯ r-1 A r-2 W r-2 + ... +
    Figure imgb0053
    A ¯ r-1 A ¯ r-2 ....A⁰W⁰;
    Figure imgb0054

    wobei r die gewünschte Genauigkeit ist, Ai ein Bit des genannten Zufallsmusters ist, Wi ein Bit eines ausgewählten der genannten Gewichtungsfaktoren ist und Zj das erzeugte gewichtete Zufalls-Bit ist.
  7. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, ferner mit:
       einer komplexen digitalen logischen Schaltung, die zu testen ist (3);
       das genannte System zum Erzeugen eines gewichteten Zufallsmusters ist auf einem einzigen Chip mit einer integrierten Schaltung hergestellt, um eine Grenzabtastungsüberprüfung der genannten digitalen logischen Schaltungen durchzuführen.
  8. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin das genannte Zufalls-Bitmuster die Kombination der genannten Multibit-Gewichtungsfaktoren in der genannten Kombinationseinrichtung steuert.
  9. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die Kombinationseinrichtung einen der genannten Multibit-Gewichtungsfaktoren mit dem genannten Zufalls-Bitmuster in einem einzigen Taktzyklus kombiniert.
  10. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, ferner mit:
       einem Register (14), das an die genannte Kombinationseinrichtung angeschlossen ist, um hierin das gewichtete Zufallsmuster zu speichern, das von der genannten Kombinationseinrichtung gebildet ist.
  11. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin der genannte Zufallsmustergenerator ein Register (17) umfaßt, um hierin das genannte Zufalls-Bitmuster zu speichern, wobei das genannte Register an die genannte Kombinationseinrichtung angeschlossen ist.
  12. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin der genannte Zufallsmustergenerator ein lineares Rückkopplungs-Schieberegister aufweist.
  13. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin der genannte Zufallsmustergenerator ein Zellular-Automatenregister aufweist.
  14. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin die Anzahl von Bits in den genannten Multibit-Gewichtungsfaktoren (W) bestimmt wird durch die gewünschte Genauigkeit für das genannte gewichtete Zufallsmuster.
  15. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin jeder der genannten Multibit-Gewichtungsfaktoren (W) eine Wahrscheinlichkeit aufweist, daß ein Einzelbit im genannten gewichteten Zufallsmuster EINS gleich ist.
  16. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin der genannte Multibit-Gewichtungsfaktor eine Wahrscheinlichkeit aufweist, daß ein Einzelbit im genannten gewichteten Zufallsmuster NULL gleich ist.
  17. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin Bits des genannten Zufalls-Bitmusters voneinander unabhängig sind.
  18. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1, worin Bits des genannten Zufalls-Bitmusters voneinander abhängig sind, und worin das genannte System zum Erzeugen eines gewichteten Zufallsmusters ferner eine Verwürfelungseinrichtung aufweist, die zwischen dem genannten Zufalls-Bitmuster-Generator und der genannten Kombinationseinrichtung angeschlossen ist, um die abhängigen Abschnitte des genannten Zufallsmusters in unabhängige Abschnitte umzuwandeln.
  19. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 18, worin jede Verwürfelungseinrichtung zusammengesetzt ist aus einer Vielzahl von Antivalenz-Gattern.
  20. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 1 in Kombination mit einem PrüfSystem (1) zum Prüfen einer im Prüfversuch befindlichen Vorrichtung.
  21. System zum Erzeugen eines gewichteten Zufallsmusters, mit den folgenden Schritten:
       Bereitstellen eines ersten Multibit-Gewichtungsfaktors (W) aus einer Vielzahl von Multibit-Gewichtungsfaktoren heraus, die in einem Ringspeicher (11) enthalten sind;
       Erzeugen eines ersten Multibit-Zufalls-Bitmusters (A);
       Kombinieren des ersten Multibit-Gewichtungsfaktors und des ersten Multibit-Zufalls-Bitmusters (13), um ein erstes Bit des gewichteten Zufallsmusters zu erzeugen; und
       Wiederholen der genannten Schritte des Bereitstellens, Erzeugens und Kombinierens auf der Grundlage zweiter und nachfolgender Multibit-Gewichtungsfaktoren sowie zweiter und nachfolgender Zufalls-Bitmuster, um zweite und nachfolgende Bits des gewichteten Zufallsmusters zu erzeugen.
  22. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der genannte Kombinationsschritt die folgenden Schritte aufweist:
       ein erstes Kombinieren eines ersten Bits aus dem Multibit-Gewichtungsfaktor (W) mit einem ersten Bit aus dem Multibit-Zufalls-Bitmuster (A), um eine erste Ausgabe zu erzeugen; und
       Wiederholen des ersten Kombinationsschrittes auf der Grundlage eines zweiten und nachfolgender Bits aus den Multibit-Gewichtungsfaktoren, auf der Grundlage eines zweiten und nachfolgender Bits aus dem Multibit-Zufallsmuster und auf der Grundlage einer ersten und nachfolgenden Ausgabe, um zweite und nachfolgende Ausgaben zu erzeugen.
  23. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der erste Kombinationsschritt den folgenden Schritt aufweist:
       Multiplexen (M) des ersten Bits aus den Multibit-Gewichtungsfaktoren (W) und einer ersten Dateneingabe (X) unter Steuerung des ersten Bits aus dem Multibit-Zufalls-Bitmuster (A), um eine erste Ausgabe (Y) zu erzeugen;
       und worin der genannte Wiederholungsschritt den folgenden Schritt aufweist:
       Multiplexen des zweiten und nachfolgenden Bits aus den Multibit-Gewichtungsfaktoren (W) und den ersten und nachfolgenden Ausgaben (Y) unter Steuerung des zweiten und nachfolgenden Bits aus dem Multibit-Zufalls-Bitmuster (A), um eine zweite und nachfolgende Ausgaben zu erzeugen.
  24. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der genannte Kombinationsschritt den folgenden Schritt aufweist:
       Kombinieren des genannten ersten Multibit-Gewichtungsfaktors des genannten ersten Zufalls-Bitmusters entsprechend der folgenden Boole'schen Funktion:

    Y⁰ = W r ;
    Figure imgb0055
    Y i = A ¯ i-1 Y i-1 + A i-1 W i-1 ,i=1...r;
    Figure imgb0056

    wobei r die gewünschte Genauigkeit ist, Ai ein Bit des genannten Zufallsmusters ist, Wi ein Bit des ausgewählten der genannten Gewichtungsfaktoren ist, Yi das Ergebnis der Kombination von Ai und Wi ist, ausgenommen Y⁰, das eingesetzt wird für Wr, und Yr das Ergebnis der abschließenden Iteration zum Erzeugen eines Bits des genannten gewichteten Zufallsmusters ist.
  25. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der genannte Kombinationsschritt den folgenden Schritt aufweit:
       Kombinieren des ersten Multibit-Gewichtungsfaktors mit dem ersten Zufalls-Bitmuster entsprechend der nachfolgenden Boole'schen Funktion:

    Z j = A ¯ r-1 A ¯ r-2 .... A ¯ ⁰²W r + A r-1 W r-1 +
    Figure imgb0057
    A ¯ r-1 A r-2 W r-2 + ... +
    Figure imgb0058
    A ¯ r-1 A ¯ r-2 ....A⁰W⁰;
    Figure imgb0059

    wobei r die gewünschte Genauigkeit ist, Ai ein Bit des genannten Zufallsmusters ist, Wi ein Bit des ausgewählten der genannten Gewichtungsfaktoren ist und Zj das erzeugte, gewichtete Zufallsmuster ist.
  26. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der Erzeugungsschritt den folgenden Schritt aufweist:
       Erzeugen eines ersten Multibit-Zufalls-Bitmusters, worin die Bits voneinander unabhängig sind.
  27. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin der genannte Erzeugungsschritt die folgenden Schritte aufweist:
       Erzeugen eines ersten Multibit-Zufalls-Bitmusters, worin die Bits voneinander abhängig sind; und
       Verwürfeln der abhängigen Bits, um ein Multibit-Zufalls-Bitmuster vorzusehen, worin die Bits voneinander unabhängig sind.
  28. System zum Erzeugen eines gewichteten Zufallsmusters nach Anspruch 21, worin das erste und nachfolgende Bits für das Zufalls-Bitmuster die Kombination des ersten und nachfolgenden Bits des Multibit-Gewichtungsfaktors steuern.
  29. System zum Erzeugen eines gewichteten Zufallsmusters nach Ansrpuch 21, worin der genannte Kombinationsschritt in einem einzigen Taktzyklus durchgeführt wird.
EP19900913270 1989-08-25 1990-08-24 Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern Expired - Lifetime EP0541537B1 (de)

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US07/398,772 US5043988A (en) 1989-08-25 1989-08-25 Method and apparatus for high precision weighted random pattern generation
US398772 1989-08-25
PCT/US1990/004832 WO1991003014A2 (en) 1989-08-25 1990-08-24 Method and apparatus for high precision weighted random pattern generation

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CA2065341C (en) 1998-05-26
JPH04507470A (ja) 1992-12-24
US5043988A (en) 1991-08-27
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WO1991003014A2 (en) 1991-03-07
CA2065341A1 (en) 1991-02-26

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