DE68928060D1 - Verfahren zur Herstellung von integrierten Schaltungen mit vergrabenen dotierten Gebieten - Google Patents

Verfahren zur Herstellung von integrierten Schaltungen mit vergrabenen dotierten Gebieten

Info

Publication number
DE68928060D1
DE68928060D1 DE68928060T DE68928060T DE68928060D1 DE 68928060 D1 DE68928060 D1 DE 68928060D1 DE 68928060 T DE68928060 T DE 68928060T DE 68928060 T DE68928060 T DE 68928060T DE 68928060 D1 DE68928060 D1 DE 68928060D1
Authority
DE
Germany
Prior art keywords
production
integrated circuits
doped regions
buried doped
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928060T
Other languages
English (en)
Other versions
DE68928060T2 (de
Inventor
David A Bell
Robert H Havemann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE68928060D1 publication Critical patent/DE68928060D1/de
Application granted granted Critical
Publication of DE68928060T2 publication Critical patent/DE68928060T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE1989628060 1988-10-31 1989-10-05 Verfahren zur Herstellung von integrierten Schaltungen mit vergrabenen dotierten Gebieten Expired - Fee Related DE68928060T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26507488A 1988-10-31 1988-10-31

Publications (2)

Publication Number Publication Date
DE68928060D1 true DE68928060D1 (de) 1997-06-26
DE68928060T2 DE68928060T2 (de) 1997-11-06

Family

ID=23008857

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1989628060 Expired - Fee Related DE68928060T2 (de) 1988-10-31 1989-10-05 Verfahren zur Herstellung von integrierten Schaltungen mit vergrabenen dotierten Gebieten

Country Status (3)

Country Link
EP (1) EP0366967B1 (de)
JP (1) JPH02244737A (de)
DE (1) DE68928060T2 (de)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0067661A1 (de) * 1981-06-15 1982-12-22 Kabushiki Kaisha Toshiba Halbleiteranordnung und Verfahren zu seiner Herstellung
JPS5827340A (ja) * 1981-08-12 1983-02-18 Hitachi Ltd 半導体集積回路装置の製造法
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
JPS60194558A (ja) * 1984-03-16 1985-10-03 Hitachi Ltd 半導体装置の製造方法
JPS60258948A (ja) * 1984-06-05 1985-12-20 Clarion Co Ltd コンプリメンタリ−ジヤンクシヨン型ｆｅｔを含む集積回路
JPS61270861A (ja) * 1985-05-27 1986-12-01 Oki Electric Ind Co Ltd Ｃｍｏｓ半導体装置の製造方法
EP0253724A1 (de) * 1986-07-16 1988-01-20 Fairchild Semiconductor Corporation Verfahren zur gleichzeitigen Herstellung von bipolaren und komplementären Feldeffekttransistoren mit einer minimalen Anzahl von Masken
EP0278619B1 (de) * 1987-01-30 1993-12-08 Texas Instruments Incorporated Verfahren zum Herstellen integrierter Strukturen aus bipolaren und CMOS-Transistoren
JPH01134962A (ja) * 1987-11-20 1989-05-26 Oki Electric Ind Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0366967A2 (de) 1990-05-09
DE68928060T2 (de) 1997-11-06
EP0366967A3 (de) 1991-09-25
JPH02244737A (ja) 1990-09-28
EP0366967B1 (de) 1997-05-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee