DE68926261D1 - Symmetrische sperrende Hochdurchbruchspannungshalbleiteranordnung und Verfahren zur Herstellung - Google Patents

Symmetrische sperrende Hochdurchbruchspannungshalbleiteranordnung und Verfahren zur Herstellung

Info

Publication number
DE68926261D1
DE68926261D1 DE68926261T DE68926261T DE68926261D1 DE 68926261 D1 DE68926261 D1 DE 68926261D1 DE 68926261 T DE68926261 T DE 68926261T DE 68926261 T DE68926261 T DE 68926261T DE 68926261 D1 DE68926261 D1 DE 68926261D1
Authority
DE
Germany
Prior art keywords
manufacture
semiconductor device
breakdown voltage
high breakdown
voltage semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68926261T
Other languages
English (en)
Other versions
DE68926261T2 (de
Inventor
Victor Albert Temple
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22703262&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68926261(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Harris Corp filed Critical Harris Corp
Application granted granted Critical
Publication of DE68926261D1 publication Critical patent/DE68926261D1/de
Publication of DE68926261T2 publication Critical patent/DE68926261T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)
  • Element Separation (AREA)
DE68926261T 1988-05-06 1989-05-05 Symmetrische sperrende Hochdurchbruchspannungshalbleiteranordnung und Verfahren zur Herstellung Expired - Fee Related DE68926261T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/190,903 US4904609A (en) 1988-05-06 1988-05-06 Method of making symmetrical blocking high voltage breakdown semiconductor device

Publications (2)

Publication Number Publication Date
DE68926261D1 true DE68926261D1 (de) 1996-05-23
DE68926261T2 DE68926261T2 (de) 1996-12-05

Family

ID=22703262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926261T Expired - Fee Related DE68926261T2 (de) 1988-05-06 1989-05-05 Symmetrische sperrende Hochdurchbruchspannungshalbleiteranordnung und Verfahren zur Herstellung

Country Status (4)

Country Link
US (1) US4904609A (de)
EP (1) EP0341075B1 (de)
JP (1) JPH0222869A (de)
DE (1) DE68926261T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4133820A1 (de) * 1991-10-12 1993-04-15 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterelementen
JP2810821B2 (ja) * 1992-03-30 1998-10-15 三菱電機株式会社 半導体装置及びその製造方法
KR940016630A (ko) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 반도체 장치 및 제조방법
US5422286A (en) * 1994-10-07 1995-06-06 United Microelectronics Corp. Process for fabricating high-voltage semiconductor power device
US5874346A (en) * 1996-05-23 1999-02-23 Advanced Micro Devices, Inc. Subtrench conductor formation with large tilt angle implant
US5767000A (en) * 1996-06-05 1998-06-16 Advanced Micro Devices, Inc. Method of manufacturing subfield conductive layer
EP0933819B1 (de) 1998-02-03 2006-04-05 Infineon Technologies AG Verfahren zur Herstellung eines beidseitig sperrenden Leistungshalbleiters
US5882986A (en) * 1998-03-30 1999-03-16 General Semiconductor, Inc. Semiconductor chips having a mesa structure provided by sawing
US6232229B1 (en) 1999-11-19 2001-05-15 Micron Technology, Inc. Microelectronic device fabricating method, integrated circuit, and intermediate construction
DE10044960B4 (de) * 2000-09-12 2006-05-18 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines Leistungshalbleiterbauelements
JP5160001B2 (ja) * 2001-04-02 2013-03-13 富士電機株式会社 半導体装置の製造方法
JP2003100666A (ja) * 2001-09-26 2003-04-04 Toshiba Corp 半導体装置の製造方法
US7776672B2 (en) * 2004-08-19 2010-08-17 Fuji Electric Systems Co., Ltd. Semiconductor device and manufacturing method thereof
JP4982948B2 (ja) * 2004-08-19 2012-07-25 富士電機株式会社 半導体装置の製造方法
DE102006009961B4 (de) * 2005-03-25 2013-07-11 Fuji Electric Co., Ltd Verfahren zur Herstellung eines Halbleiterbauteils
DE102005023668B3 (de) * 2005-05-23 2006-11-09 Infineon Technologies Ag Halbleiterbauelement mit einer Randstruktur mit Spannungsdurchbruch im linearen Bereich
US8153464B2 (en) * 2005-10-18 2012-04-10 International Rectifier Corporation Wafer singulation process
JP5002974B2 (ja) * 2006-02-02 2012-08-15 富士電機株式会社 半導体装置
JP4901300B2 (ja) * 2006-05-19 2012-03-21 新電元工業株式会社 半導体装置の製造方法
JP5124999B2 (ja) * 2006-06-15 2013-01-23 富士電機株式会社 半導体装置およびその製造方法
US7586156B2 (en) * 2006-07-26 2009-09-08 Fairchild Semiconductor Corporation Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device
JP4994147B2 (ja) * 2007-08-07 2012-08-08 日本インター株式会社 半導体チップの製造方法および使用方法
WO2010065428A2 (en) * 2008-12-01 2010-06-10 Maxpower Semiconductor Inc. Mos-gated power devices, methods, and integrated circuits
US8106487B2 (en) 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension
JP2011187916A (ja) 2010-02-12 2011-09-22 Fuji Electric Co Ltd 逆阻止型絶縁ゲートバイポーラトランジスタの製造方法
US8361884B2 (en) * 2010-06-22 2013-01-29 Infineon Technologies Ag Plasma dicing and semiconductor devices formed thereof
JP5549532B2 (ja) * 2010-10-21 2014-07-16 富士電機株式会社 半導体装置の製造方法
JP5692241B2 (ja) 2011-01-18 2015-04-01 富士電機株式会社 逆阻止型半導体素子の製造方法
JP5655931B2 (ja) 2011-03-14 2015-01-21 富士電機株式会社 半導体装置の製造方法
JP5866827B2 (ja) 2011-06-30 2016-02-24 富士電機株式会社 逆阻止型絶縁ゲート型バイポーラトランジスタの製造方法
DE102011112659B4 (de) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
JP5445563B2 (ja) * 2011-11-21 2014-03-19 富士電機株式会社 半導体装置の製造方法
US9006027B2 (en) 2012-09-11 2015-04-14 General Electric Company Systems and methods for terminating junctions in wide bandgap semiconductor devices
US9704718B2 (en) * 2013-03-22 2017-07-11 Infineon Technologies Austria Ag Method for manufacturing a silicon carbide device and a silicon carbide device
US9590033B1 (en) * 2015-11-20 2017-03-07 Ixys Corporation Trench separation diffusion for high voltage device
US9704832B1 (en) 2016-02-29 2017-07-11 Ixys Corporation Die stack assembly using an edge separation structure for connectivity through a die of the stack

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3394037A (en) * 1965-05-28 1968-07-23 Motorola Inc Method of making a semiconductor device by masking and diffusion
US3847687A (en) * 1972-11-15 1974-11-12 Motorola Inc Methods of forming self aligned transistor structure having polycrystalline contacts
DE2633324C2 (de) * 1976-07-24 1983-09-15 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Verfahren zum Herstellen von Halbleiterbauelementen hoher Sperrspannungsbelastbarkeit
JPS5356972A (en) * 1976-11-01 1978-05-23 Mitsubishi Electric Corp Mesa type semiconductor device
US4364073A (en) * 1980-03-25 1982-12-14 Rca Corporation Power MOSFET with an anode region
GB2089119A (en) * 1980-12-10 1982-06-16 Philips Electronic Associated High voltage semiconductor devices
US4652895A (en) * 1982-08-09 1987-03-24 Harris Corporation Zener structures with connections to buried layer
US4555845A (en) * 1982-10-13 1985-12-03 Westinghouse Electric Corp. Temperature stable self-protected thyristor and method of producing
US4514898A (en) * 1983-02-18 1985-05-07 Westinghouse Electric Corp. Method of making a self protected thyristor
US4516315A (en) * 1983-05-09 1985-05-14 Westinghouse Electric Corp. Method of making a self-protected thyristor
US4622569A (en) * 1984-06-08 1986-11-11 Eaton Corporation Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means
FR2574595B1 (fr) * 1984-12-11 1987-01-16 Silicium Semiconducteur Ssc Diac a electrodes coplanaires
US4651178A (en) * 1985-05-31 1987-03-17 Rca Corporation Dual inverse zener diode with buried junctions

Also Published As

Publication number Publication date
US4904609A (en) 1990-02-27
DE68926261T2 (de) 1996-12-05
EP0341075A2 (de) 1989-11-08
EP0341075A3 (en) 1990-05-02
JPH0222869A (ja) 1990-01-25
EP0341075B1 (de) 1996-04-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee