DE68923531T2 - Verfahren und vorrichtung zum speicherselbsttest. - Google Patents

Verfahren und vorrichtung zum speicherselbsttest.

Info

Publication number
DE68923531T2
DE68923531T2 DE68923531T DE68923531T DE68923531T2 DE 68923531 T2 DE68923531 T2 DE 68923531T2 DE 68923531 T DE68923531 T DE 68923531T DE 68923531 T DE68923531 T DE 68923531T DE 68923531 T2 DE68923531 T2 DE 68923531T2
Authority
DE
Germany
Prior art keywords
memory
series
data
data words
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923531T
Other languages
English (en)
Other versions
DE68923531D1 (de
Inventor
Donald Pierce
Edward Utzig
Robert Crouse
Noreen Hession
Donald Smelser
Hansel Collins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68923531D1 publication Critical patent/DE68923531D1/de
Application granted granted Critical
Publication of DE68923531T2 publication Critical patent/DE68923531T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36Data generation devices, e.g. data inverters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Debugging And Monitoring (AREA)
DE68923531T 1988-04-01 1989-03-15 Verfahren und vorrichtung zum speicherselbsttest. Expired - Fee Related DE68923531T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17669988A 1988-04-01 1988-04-01
PCT/US1989/001036 WO1989009471A2 (en) 1988-04-01 1989-03-15 Memory selftest method and apparatus

Publications (2)

Publication Number Publication Date
DE68923531D1 DE68923531D1 (de) 1995-08-24
DE68923531T2 true DE68923531T2 (de) 1996-04-04

Family

ID=22645472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923531T Expired - Fee Related DE68923531T2 (de) 1988-04-01 1989-03-15 Verfahren und vorrichtung zum speicherselbsttest.

Country Status (5)

Country Link
EP (1) EP0366757B1 (de)
JP (1) JP2740899B2 (de)
CA (1) CA1304821C (de)
DE (1) DE68923531T2 (de)
WO (1) WO1989009471A2 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10135583B4 (de) * 2001-07-20 2004-05-06 Infineon Technologies Ag Datengenerator zur Erzeugung von Testdaten für wortorientierte Halbleiterspeicher
DE102004051344A1 (de) * 2004-10-21 2006-05-04 Infineon Technologies Ag Halbleiter-Bauelement-Test-Einrichtung mit Schieberegister, sowie Halbleiter-Bauelement-Test-Verfahren
DE102004051346A1 (de) * 2004-10-21 2006-05-04 Infineon Technologies Ag Halbleiter-Bauelement-Test-Einrichtung, insbesondere Daten-Zwischenspeicher-Bauelement mit Halbleiter-Bauelement-Test-Einrichtung, sowie Halbleiter-Bauelement-Test-Verfahren

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0441088A1 (de) * 1990-01-24 1991-08-14 International Business Machines Corporation In Speicherkarte-residenter Diagnosetest
US5274648A (en) * 1990-01-24 1993-12-28 International Business Machines Corporation Memory card resident diagnostic testing
JP3849884B2 (ja) * 1995-06-09 2006-11-22 富士通株式会社 2進数の1つのシーケンスを生成する装置、記憶モジュール内の障害に対するテストを行う方法、および記憶モジュールに対するテストを行うシステム
US6477673B1 (en) * 1999-07-30 2002-11-05 Stmicroelectronics, Inc. Structure and method with which to generate data background patterns for testing random-access-memories
CN111044886B (zh) * 2019-12-09 2022-05-13 北京时代民芯科技有限公司 一种ddr2/3 phy bist数据通道测试向量生成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831762B2 (ja) * 1974-08-21 1983-07-08 横河電機株式会社 ランダムシンゴウハツセイカイロ
JPS5199439A (de) * 1975-02-28 1976-09-02 Fujitsu Ltd
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
JPS54132145A (en) * 1978-04-06 1979-10-13 Nec Corp False random code generator
DE3069611D1 (en) * 1979-12-27 1984-12-13 Fujitsu Ltd Apparatus and method for testing semiconductor memory devices
JPS58101515A (ja) * 1981-12-14 1983-06-16 Agency Of Ind Science & Technol 最大周期列信号の初期値設定回路
JPS59166879A (ja) * 1983-03-14 1984-09-20 Nec Corp 集積回路装置
US4715034A (en) * 1985-03-04 1987-12-22 John Fluke Mfg. Co., Inc. Method of and system for fast functional testing of random access memories

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10135583B4 (de) * 2001-07-20 2004-05-06 Infineon Technologies Ag Datengenerator zur Erzeugung von Testdaten für wortorientierte Halbleiterspeicher
DE102004051344A1 (de) * 2004-10-21 2006-05-04 Infineon Technologies Ag Halbleiter-Bauelement-Test-Einrichtung mit Schieberegister, sowie Halbleiter-Bauelement-Test-Verfahren
DE102004051346A1 (de) * 2004-10-21 2006-05-04 Infineon Technologies Ag Halbleiter-Bauelement-Test-Einrichtung, insbesondere Daten-Zwischenspeicher-Bauelement mit Halbleiter-Bauelement-Test-Einrichtung, sowie Halbleiter-Bauelement-Test-Verfahren
US7415649B2 (en) 2004-10-21 2008-08-19 Infineon Technologies Ag Semi-conductor component test device with shift register, and semi-conductor component test procedure
US7421629B2 (en) 2004-10-21 2008-09-02 Infineon Technologies Ag Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure

Also Published As

Publication number Publication date
JP2740899B2 (ja) 1998-04-15
DE68923531D1 (de) 1995-08-24
WO1989009471A2 (en) 1989-10-05
WO1989009471A3 (en) 1989-11-16
EP0366757A1 (de) 1990-05-09
EP0366757B1 (de) 1995-07-19
JPH0277860A (ja) 1990-03-16
CA1304821C (en) 1992-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee