DE68916563T2 - Speicheranordnung mit Vorhersage der Bausteinauswahl. - Google Patents

Speicheranordnung mit Vorhersage der Bausteinauswahl.

Info

Publication number
DE68916563T2
DE68916563T2 DE68916563T DE68916563T DE68916563T2 DE 68916563 T2 DE68916563 T2 DE 68916563T2 DE 68916563 T DE68916563 T DE 68916563T DE 68916563 T DE68916563 T DE 68916563T DE 68916563 T2 DE68916563 T2 DE 68916563T2
Authority
DE
Germany
Prior art keywords
prediction
block selection
memory arrangement
memory
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916563T
Other languages
English (en)
Other versions
DE68916563D1 (de
Inventor
Ferruccio Zulian
Enrico Porro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA
Publication of DE68916563D1 publication Critical patent/DE68916563D1/de
Application granted granted Critical
Publication of DE68916563T2 publication Critical patent/DE68916563T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
DE68916563T 1988-03-15 1989-02-25 Speicheranordnung mit Vorhersage der Bausteinauswahl. Expired - Fee Related DE68916563T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8819773A IT1216087B (it) 1988-03-15 1988-03-15 Sistema di memoria con selezione predittiva di modulo.

Publications (2)

Publication Number Publication Date
DE68916563D1 DE68916563D1 (de) 1994-08-11
DE68916563T2 true DE68916563T2 (de) 1994-12-22

Family

ID=11161105

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916563T Expired - Fee Related DE68916563T2 (de) 1988-03-15 1989-02-25 Speicheranordnung mit Vorhersage der Bausteinauswahl.

Country Status (4)

Country Link
US (1) US5060188A (de)
EP (1) EP0332910B1 (de)
DE (1) DE68916563T2 (de)
IT (1) IT1216087B (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04143819A (ja) * 1989-12-15 1992-05-18 Hitachi Ltd 消費電力制御方法、半導体集積回路装置およびマイクロプロセツサ
US5392414A (en) * 1992-06-30 1995-02-21 Sun Microsystems, Inc. Rapid data retrieval from data storage structures using prior access predictive annotations
US5588128A (en) * 1993-04-02 1996-12-24 Vlsi Technology, Inc. Dynamic direction look ahead read buffer
US5548739A (en) * 1993-11-04 1996-08-20 Sun Microsystems, Inc. Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations
US5603010A (en) * 1995-12-28 1997-02-11 Intel Corporation Performing speculative system memory reads prior to decoding device code
EP1197867A3 (de) * 1996-06-06 2005-12-14 Freescale Semiconductor, Inc. Verfahren zum Speicherzugriff
JPH11272509A (ja) * 1998-03-24 1999-10-08 Nec Ic Microcomput Syst Ltd 半導体集積回路
US6253276B1 (en) * 1998-06-30 2001-06-26 Micron Technology, Inc. Apparatus for adaptive decoding of memory addresses
FR2808605B1 (fr) * 2000-05-02 2003-10-10 Canon Kk Procede et dispositif de transfert de donnees entre deux memoires
FR2823874B1 (fr) * 2001-04-20 2003-10-31 St Microelectronics Sa Procede d'adressage de memoire optimise
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US9336164B2 (en) * 2012-10-04 2016-05-10 Applied Micro Circuits Corporation Scheduling memory banks based on memory access patterns
KR20160038034A (ko) 2013-07-27 2016-04-06 넷리스트 인코포레이티드 로컬 동기화를 갖는 메모리 모듈
US10956078B2 (en) * 2018-03-27 2021-03-23 EMC IP Holding Company LLC Storage system with loopback replication process providing object-dependent slice assignment
US10866969B2 (en) 2018-03-28 2020-12-15 EMC IP Holding Company LLC Storage system with loopback replication process providing unique identifiers for collision-free object pairing

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156905A (en) * 1974-02-28 1979-05-29 Ncr Corporation Method and apparatus for improving access speed in a random access memory
US4042913A (en) * 1976-04-30 1977-08-16 International Business Machines Corporation Address key register load/store instruction system
US4296467A (en) * 1978-07-03 1981-10-20 Honeywell Information Systems Inc. Rotating chip selection technique and apparatus
DE2842548A1 (de) * 1978-09-29 1980-04-10 Siemens Ag Programmierbare speicherschutzlogik fuer mikroprozessorsysteme
FR2443723A1 (fr) * 1978-12-06 1980-07-04 Cii Honeywell Bull Dispositif de reduction du temps d'acces aux informations contenues dans une memoire d'un systeme de traitement de l'information
US4280176A (en) * 1978-12-26 1981-07-21 International Business Machines Corporation Memory configuration, address interleaving, relocation and access control system
JPS5943786B2 (ja) * 1979-03-30 1984-10-24 パナフアコム株式会社 記憶装置のアクセス方式
US4323965A (en) * 1980-01-08 1982-04-06 Honeywell Information Systems Inc. Sequential chip select decode apparatus and method
US4408273A (en) * 1980-05-27 1983-10-04 International Business Machines Corporation Method and means for cataloging data sets using dual keyed data sets and direct pointers
IT1153611B (it) * 1982-11-04 1987-01-14 Honeywell Inf Systems Procedimento di mappatura della memoria in sistema di elaborazione dati
US4531200A (en) * 1982-12-02 1985-07-23 International Business Machines Corporation Indexed-indirect addressing using prefix codes
US4809156A (en) * 1984-03-19 1989-02-28 Trw Inc. Address generator circuit
CA1234224A (en) * 1985-05-28 1988-03-15 Boleslav Sykora Computer memory management system
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4831522A (en) * 1987-02-17 1989-05-16 Microlytics, Inc. Circuit and method for page addressing read only memory
US4961172A (en) * 1988-08-11 1990-10-02 Waferscale Integration, Inc. Decoder for a memory address bus
US4932001A (en) * 1988-10-12 1990-06-05 Advanced Micro Devices, Inc. Reducing power consumption in on-chip memory devices

Also Published As

Publication number Publication date
EP0332910B1 (de) 1994-07-06
IT8819773A0 (it) 1988-03-15
EP0332910A2 (de) 1989-09-20
DE68916563D1 (de) 1994-08-11
EP0332910A3 (de) 1991-03-27
US5060188A (en) 1991-10-22
IT1216087B (it) 1990-02-22

Similar Documents

Publication Publication Date Title
DE68916563D1 (de) Speicheranordnung mit Vorhersage der Bausteinauswahl.
DE68919962D1 (de) Kombinierte kryogen-mechanische Gefriereinrichtung.
NO892844D0 (no) Engangsforskalingselement.
DE68912458T2 (de) Speicherprüfgerät.
DE68909922D1 (de) Thermochromische gemische.
DE68906102T2 (de) Kuehlbehaelter.
NO892294L (no) Polypeptidforbindelser.
FI893541A0 (fi) Nytt uttryckningssystem.
DE68915608D1 (de) Speicherarchitektur.
FI893422A (fi) Madrasskonstruktion foer vattenbaedd.
NO893775L (no) Substituerte tienepyraner.
NO894589D0 (no) Substituerte oksadiaminobutaner.
DE68924860T2 (de) Erweiterte Speicheranordnung.
FI881812A0 (fi) Foerfarande foer regenerering av betningssyror i zinkgalvaniseringsprocesser.
DE58907370D1 (de) Substituierte Azolylmethyloxirane.
DE3865192D1 (de) Speichereinheit.
DE58903542D1 (de) Konstruktionsprofil.
TR24177A (tr) Fenoksifenil ikame edilmis tetrazolinonlar.
DE68902749T2 (de) Einfaedler mit nadelhaltender einkerbung.
FI880759A0 (fi) Anordning foer neddoppning av foeremaol i vaetska.
ATE96083T1 (de) Verbundener gegenstand.
FI883463A (fi) Anordning foer undervattensarbete.
FI880729A0 (fi) Fuktbestaendiga hudvaordskompositioner.
FI882673A (fi) Bogseringsanordning/block.
FI880690A0 (fi) Fullstaendigare variant av tandborste.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee