FR2823874B1 - Procede d'adressage de memoire optimise - Google Patents

Procede d'adressage de memoire optimise

Info

Publication number
FR2823874B1
FR2823874B1 FR0105405A FR0105405A FR2823874B1 FR 2823874 B1 FR2823874 B1 FR 2823874B1 FR 0105405 A FR0105405 A FR 0105405A FR 0105405 A FR0105405 A FR 0105405A FR 2823874 B1 FR2823874 B1 FR 2823874B1
Authority
FR
France
Prior art keywords
addressing method
memory addressing
optimized memory
optimized
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0105405A
Other languages
English (en)
Other versions
FR2823874A1 (fr
Inventor
Jean Paul Henriques
Fabrice Devaux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0105405A priority Critical patent/FR2823874B1/fr
Priority to US10/475,485 priority patent/US7966473B2/en
Priority to PCT/FR2002/001328 priority patent/WO2002086700A1/fr
Priority to EP02727670A priority patent/EP1381940A1/fr
Publication of FR2823874A1 publication Critical patent/FR2823874A1/fr
Application granted granted Critical
Publication of FR2823874B1 publication Critical patent/FR2823874B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
FR0105405A 2001-04-20 2001-04-20 Procede d'adressage de memoire optimise Expired - Fee Related FR2823874B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0105405A FR2823874B1 (fr) 2001-04-20 2001-04-20 Procede d'adressage de memoire optimise
US10/475,485 US7966473B2 (en) 2001-04-20 2002-04-17 Optimised storage addressing method
PCT/FR2002/001328 WO2002086700A1 (fr) 2001-04-20 2002-04-17 Procede d'adressage de memoire optimise
EP02727670A EP1381940A1 (fr) 2001-04-20 2002-04-17 Procede d'adressage de memoire optimise

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0105405A FR2823874B1 (fr) 2001-04-20 2001-04-20 Procede d'adressage de memoire optimise

Publications (2)

Publication Number Publication Date
FR2823874A1 FR2823874A1 (fr) 2002-10-25
FR2823874B1 true FR2823874B1 (fr) 2003-10-31

Family

ID=8862553

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0105405A Expired - Fee Related FR2823874B1 (fr) 2001-04-20 2001-04-20 Procede d'adressage de memoire optimise

Country Status (4)

Country Link
US (1) US7966473B2 (fr)
EP (1) EP1381940A1 (fr)
FR (1) FR2823874B1 (fr)
WO (1) WO2002086700A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9116824B2 (en) * 2013-03-15 2015-08-25 Sandisk Technologies Inc. System and method to reduce read latency of a data storage device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4236205A (en) * 1978-10-23 1980-11-25 International Business Machines Corporation Access-time reduction control circuit and process for digital storage devices
IT1216087B (it) * 1988-03-15 1990-02-22 Honeywell Bull Spa Sistema di memoria con selezione predittiva di modulo.
US5611065A (en) * 1994-09-14 1997-03-11 Unisys Corporation Address prediction for relative-to-absolute addressing
US5987561A (en) * 1995-08-31 1999-11-16 Advanced Micro Devices, Inc. Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5710914A (en) * 1995-12-29 1998-01-20 Atmel Corporation Digital signal processing method and system implementing pipelined read and write operations
US6101577A (en) * 1997-09-15 2000-08-08 Advanced Micro Devices, Inc. Pipelined instruction cache and branch prediction mechanism therefor
US6253276B1 (en) * 1998-06-30 2001-06-26 Micron Technology, Inc. Apparatus for adaptive decoding of memory addresses
US6647490B2 (en) * 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6651162B1 (en) * 1999-11-04 2003-11-18 International Business Machines Corporation Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache
US6694421B2 (en) * 1999-12-29 2004-02-17 Intel Corporation Cache memory bank access prediction
US7139903B2 (en) * 2000-12-19 2006-11-21 Hewlett-Packard Development Company, L.P. Conflict free parallel read access to a bank interleaved branch predictor in a processor
US7062638B2 (en) * 2000-12-29 2006-06-13 Intel Corporation Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores
US7181598B2 (en) * 2002-05-17 2007-02-20 Intel Corporation Prediction of load-store dependencies in a processing agent

Also Published As

Publication number Publication date
FR2823874A1 (fr) 2002-10-25
EP1381940A1 (fr) 2004-01-21
US7966473B2 (en) 2011-06-21
WO2002086700A1 (fr) 2002-10-31
US20040199738A1 (en) 2004-10-07

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20091231