DE68915123D1 - Halbleiterspeicheranordnung, die an der Vorstufe eines Adressendekodierers einen Pegelschieber zur Erzeugung einer Programmierspannung hat. - Google Patents

Halbleiterspeicheranordnung, die an der Vorstufe eines Adressendekodierers einen Pegelschieber zur Erzeugung einer Programmierspannung hat.

Info

Publication number
DE68915123D1
DE68915123D1 DE68915123T DE68915123T DE68915123D1 DE 68915123 D1 DE68915123 D1 DE 68915123D1 DE 68915123 T DE68915123 T DE 68915123T DE 68915123 T DE68915123 T DE 68915123T DE 68915123 D1 DE68915123 D1 DE 68915123D1
Authority
DE
Germany
Prior art keywords
generating
semiconductor memory
level shifter
address decoder
programming voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68915123T
Other languages
English (en)
Other versions
DE68915123T2 (de
Inventor
Osamu C O Intellectu Matsumoto
Yuji C O Intellectual P Nakano
Isao C O Intellectual Prop Abe
Mika C O Intellectual Pr Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE68915123D1 publication Critical patent/DE68915123D1/de
Application granted granted Critical
Publication of DE68915123T2 publication Critical patent/DE68915123T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
DE68915123T 1988-11-21 1989-11-08 Halbleiterspeicheranordnung, die an der Vorstufe eines Adressendekodierers einen Pegelschieber zur Erzeugung einer Programmierspannung hat. Expired - Fee Related DE68915123T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29418588A JPH0713880B2 (ja) 1988-11-21 1988-11-21 不揮発性半導体メモリ

Publications (2)

Publication Number Publication Date
DE68915123D1 true DE68915123D1 (de) 1994-06-09
DE68915123T2 DE68915123T2 (de) 1994-09-15

Family

ID=17804414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68915123T Expired - Fee Related DE68915123T2 (de) 1988-11-21 1989-11-08 Halbleiterspeicheranordnung, die an der Vorstufe eines Adressendekodierers einen Pegelschieber zur Erzeugung einer Programmierspannung hat.

Country Status (5)

Country Link
US (1) US5031149A (de)
EP (1) EP0370308B1 (de)
JP (1) JPH0713880B2 (de)
KR (1) KR930000159B1 (de)
DE (1) DE68915123T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930002574B1 (ko) * 1990-03-09 1993-04-03 금성일렉트론 주식회사 워드라인 구동회로
GB2243233A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM word line driver
US5751643A (en) * 1990-04-06 1998-05-12 Mosaid Technologies Incorporated Dynamic memory word line driver
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
GB9007791D0 (en) 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
JP2679381B2 (ja) * 1990-08-30 1997-11-19 日本電気株式会社 半導体記憶集積回路
US5274600A (en) * 1990-12-13 1993-12-28 Texas Instruments Incorporated First-in first-out memory
US5202855A (en) * 1991-01-14 1993-04-13 Motorola, Inc. DRAM with a controlled boosted voltage level shifting driver
JPH05128866A (ja) * 1991-10-31 1993-05-25 Toshiba Corp ランダムアクセスメモリの書き込み、読出し制御回路
US5285407A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Memory circuit for spatial light modulator
JP2708333B2 (ja) * 1992-09-02 1998-02-04 株式会社東芝 レベルシフタ回路
US5644533A (en) * 1992-11-02 1997-07-01 Nvx Corporation Flash memory system, and methods of constructing and utilizing same
JP3743453B2 (ja) * 1993-01-27 2006-02-08 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3085824B2 (ja) * 1993-05-20 2000-09-11 富士写真フイルム株式会社 メモリ制御装置
US5511026A (en) * 1993-12-01 1996-04-23 Advanced Micro Devices, Inc. Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories
US5450357A (en) * 1994-04-01 1995-09-12 Texas Instruments Incorporated Level shifter circuit
JPH08241240A (ja) * 1995-03-03 1996-09-17 Toshiba Corp コンピュータシステム
KR100560653B1 (ko) * 2003-02-10 2006-03-16 삼성전자주식회사 듀얼 절연막 체계를 갖는 반도체 집적 회로 장치
JP2006196061A (ja) * 2005-01-12 2006-07-27 Toshiba Corp 電圧切換回路、及びこれを用いた半導体記憶装置
US7729155B2 (en) * 2005-12-30 2010-06-01 Stmicroelectronics Pvt. Ltd. High speed, low power, low leakage read only memory
US8064255B2 (en) 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime
US8059458B2 (en) * 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4289982A (en) * 1979-06-28 1981-09-15 Motorola, Inc. Apparatus for programming a dynamic EPROM
US4433257A (en) * 1980-03-03 1984-02-21 Tokyo Shibaura Denki Kabushiki Kaisha Voltage supply for operating a plurality of changing transistors in a manner which reduces minority carrier disruption of adjacent memory cells
JPS57192067A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Erasable and programmable read only memory unit
US4446536A (en) * 1982-06-21 1984-05-01 Mcdonnell Douglas Corporation Complementary metal oxide semiconductors address drive circuit
JPS61151898A (ja) * 1984-12-26 1986-07-10 Fujitsu Ltd 半導体記憶装置におけるワ−ド線ドライバ回路
US4642798A (en) * 1985-10-01 1987-02-10 Intel Corporation CMOS E2 PROM decoding circuit

Also Published As

Publication number Publication date
EP0370308A2 (de) 1990-05-30
JPH02141994A (ja) 1990-05-31
JPH0713880B2 (ja) 1995-02-15
DE68915123T2 (de) 1994-09-15
EP0370308B1 (de) 1994-05-04
US5031149A (en) 1991-07-09
KR930000159B1 (ko) 1993-01-09
KR900008676A (ko) 1990-06-03
EP0370308A3 (de) 1992-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee