DE68914548D1 - Pufferschaltung für logische Pegelumsetzung. - Google Patents

Pufferschaltung für logische Pegelumsetzung.

Info

Publication number
DE68914548D1
DE68914548D1 DE68914548T DE68914548T DE68914548D1 DE 68914548 D1 DE68914548 D1 DE 68914548D1 DE 68914548 T DE68914548 T DE 68914548T DE 68914548 T DE68914548 T DE 68914548T DE 68914548 D1 DE68914548 D1 DE 68914548D1
Authority
DE
Germany
Prior art keywords
buffer circuit
level conversion
logical level
logical
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68914548T
Other languages
English (en)
Inventor
Kiyoshi Kajii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68914548D1 publication Critical patent/DE68914548D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE68914548T 1988-08-30 1989-08-29 Pufferschaltung für logische Pegelumsetzung. Expired - Lifetime DE68914548D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63216732A JPH0263319A (ja) 1988-08-30 1988-08-30 入力バッファ

Publications (1)

Publication Number Publication Date
DE68914548D1 true DE68914548D1 (de) 1994-05-19

Family

ID=16693062

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68914548T Expired - Lifetime DE68914548D1 (de) 1988-08-30 1989-08-29 Pufferschaltung für logische Pegelumsetzung.

Country Status (5)

Country Link
US (1) US5051626A (de)
EP (1) EP0356986B1 (de)
JP (1) JPH0263319A (de)
KR (1) KR920005359B1 (de)
DE (1) DE68914548D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0452675B1 (de) * 1990-03-15 1996-05-22 Fujitsu Limited Pufferschaltung zur logischen Pegelumsetzung
JPH0595267A (ja) * 1991-10-02 1993-04-16 Sumitomo Electric Ind Ltd 半導体論理装置
JP3365804B2 (ja) * 1993-01-12 2003-01-14 株式会社日立製作所 通信回線駆動回路、及びインタフェース用ｌｓｉ、並びに通信端末装置
US5420527A (en) * 1994-04-06 1995-05-30 Itt Corporation Temperature and supply insensitive TTL or CMOS to 0/-5 V translator
JPH08204536A (ja) * 1995-01-20 1996-08-09 Fujitsu Ltd インタフェース回路及びレベル変換回路
US6147540A (en) 1998-08-31 2000-11-14 Motorola Inc. High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
KR20030007299A (ko) * 2002-12-04 2003-01-23 (주) 바이탈인터내셔날 발광장치를 구비하는 가방
US8154320B1 (en) * 2009-03-24 2012-04-10 Lockheed Martin Corporation Voltage level shifter
CN111786642A (zh) * 2020-07-10 2020-10-16 无锡英迪芯微电子科技股份有限公司 具有端口电压保护功能的推挽结构端口输出电路
CN114070297A (zh) * 2020-08-05 2022-02-18 圣邦微电子（北京）股份有限公司 微功耗的电平翻转电路及降低电路中瞬态电流的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550743A (en) * 1978-10-11 1980-04-12 Fujitsu Ltd Level shift circuit
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
US4791322A (en) * 1987-05-19 1988-12-13 Gazelle Microcircuits, Inc. TTL compatible input buffer
US4779015A (en) * 1987-05-26 1988-10-18 International Business Machines Corporation Low voltage swing CMOS receiver circuit
US4767951A (en) * 1987-06-30 1988-08-30 Hewlett-Packard Company ECL to NMOS converter
US4835419A (en) * 1987-10-30 1989-05-30 International Business Machines Corporation Source-follower emitter-coupled-logic receiver circuit

Also Published As

Publication number Publication date
EP0356986A2 (de) 1990-03-07
JPH0263319A (ja) 1990-03-02
KR920005359B1 (ko) 1992-07-02
KR900004111A (ko) 1990-03-27
US5051626A (en) 1991-09-24
EP0356986A3 (en) 1990-09-19
EP0356986B1 (de) 1994-04-13

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Legal Events

Date Code Title Description
8332 No legal effect for de