DE60330807D1 - - Google Patents

Info

Publication number
DE60330807D1
DE60330807D1 DE60330807T DE60330807T DE60330807D1 DE 60330807 D1 DE60330807 D1 DE 60330807D1 DE 60330807 T DE60330807 T DE 60330807T DE 60330807 T DE60330807 T DE 60330807T DE 60330807 D1 DE60330807 D1 DE 60330807D1
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60330807T
Inventor
Michael D Eby
Gregory P Mikol
James E Demaris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Application granted granted Critical
Publication of DE60330807D1 publication Critical patent/DE60330807D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE60330807T 2002-12-09 2003-10-21 Expired - Lifetime DE60330807D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/315,523 US6744659B1 (en) 2002-12-09 2002-12-09 Source-biased memory cell array
PCT/US2003/033526 WO2004053881A2 (en) 2002-12-09 2003-10-21 Source-biased memory cell array

Publications (1)

Publication Number Publication Date
DE60330807D1 true DE60330807D1 (de) 2010-02-11

Family

ID=32325901

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60330807T Expired - Lifetime DE60330807D1 (de) 2002-12-09 2003-10-21

Country Status (8)

Country Link
US (1) US6744659B1 (de)
EP (1) EP1581952B1 (de)
JP (1) JP2006509325A (de)
KR (1) KR20050087827A (de)
CN (1) CN1742342B (de)
AU (1) AU2003285948A1 (de)
DE (1) DE60330807D1 (de)
WO (1) WO2004053881A2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4388274B2 (ja) 2002-12-24 2009-12-24 株式会社ルネサステクノロジ 半導体記憶装置
US6934181B2 (en) * 2003-02-06 2005-08-23 International Business Machines Corporation Reducing sub-threshold leakage in a memory array
EP1511042B1 (de) * 2003-08-27 2012-12-05 STMicroelectronics Srl Phasenübergangsspeicheranordnung mit Vorspannung von nicht-selektierten Bit-Leitungen
KR100604876B1 (ko) * 2004-07-02 2006-07-31 삼성전자주식회사 다양한 ｐｖｔ 변화에 대해서도 안정적인 버츄얼 레일스킴을 적용한 ｓｒａｍ 장치
KR101185619B1 (ko) * 2004-07-06 2012-09-24 케네트, 인크 전압 랜덤 액세스 메모리
JP4553185B2 (ja) * 2004-09-15 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP4912016B2 (ja) * 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2007035115A (ja) * 2005-07-25 2007-02-08 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100662215B1 (ko) 2005-07-28 2006-12-28 민경식 에스램 회로 및 그 구동방법
US7400532B2 (en) * 2006-02-16 2008-07-15 Micron Technology, Inc. Programming method to reduce gate coupling interference for non-volatile memory
US7916556B2 (en) * 2007-01-09 2011-03-29 Sony Corporation Semiconductor memory device, sense amplifier circuit and memory cell reading method using a threshold correction circuitry
US7782655B2 (en) * 2008-07-01 2010-08-24 Jeng-Jye Shau Ultra-low power hybrid sub-threshold circuits
US8164969B2 (en) * 2008-07-01 2012-04-24 Jeng-Jye Shau Ultra-low power hybrid circuits
US20100149884A1 (en) * 2008-11-11 2010-06-17 Stmicroelectronics Pvt. Ltd. Reduction of power consumption in a memory device during sleep mode of operation
US8792294B2 (en) * 2012-01-09 2014-07-29 Mediatek Inc. DRAM and access and operating method thereof
CN103778953B (zh) * 2012-10-18 2017-03-15 中芯国际集成电路制造(上海)有限公司 Sram的存储单元
US9806019B2 (en) 2015-09-22 2017-10-31 Nxp Usa, Inc. Integrated circuit with power saving feature
US10446225B1 (en) 2018-04-30 2019-10-15 Nxp Usa, Inc. Memory system having a source bias circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543500A (en) * 1978-09-22 1985-09-24 Texas Instruments Incorporated High performance dynamic sense amplifier voltage boost for row address lines
US4754167A (en) 1985-04-04 1988-06-28 Cecil Conkle Programmable reference voltage generator for a read only memory
JPH07111824B2 (ja) * 1986-12-15 1995-11-29 株式会社東芝 半導体メモリ
US5159571A (en) * 1987-12-29 1992-10-27 Hitachi, Ltd. Semiconductor memory with a circuit for testing characteristics of flip-flops including selectively applied power supply voltages
CN1223441A (zh) * 1998-01-09 1999-07-21 日本电气株式会社 能够减少流过衬底的漏电流的半导体存储器件
KR100294447B1 (ko) 1998-06-29 2001-09-17 윤종용 불휘발성반도체메모리장치
US6172901B1 (en) * 1999-12-30 2001-01-09 Stmicroelectronics, S.R.L. Low power static random access memory and method for writing to same
US6560139B2 (en) * 2001-03-05 2003-05-06 Intel Corporation Low leakage current SRAM array
US6618295B2 (en) * 2001-03-21 2003-09-09 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array

Also Published As

Publication number Publication date
JP2006509325A (ja) 2006-03-16
AU2003285948A1 (en) 2004-06-30
KR20050087827A (ko) 2005-08-31
WO2004053881A2 (en) 2004-06-24
US20040109361A1 (en) 2004-06-10
CN1742342A (zh) 2006-03-01
US6744659B1 (en) 2004-06-01
EP1581952A2 (de) 2005-10-05
AU2003285948A8 (en) 2004-06-30
EP1581952B1 (de) 2009-12-30
CN1742342B (zh) 2010-10-06
WO2004053881A3 (en) 2005-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition