DE60323232D1 - Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen - Google Patents

Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen

Info

Publication number
DE60323232D1
DE60323232D1 DE60323232T DE60323232T DE60323232D1 DE 60323232 D1 DE60323232 D1 DE 60323232D1 DE 60323232 T DE60323232 T DE 60323232T DE 60323232 T DE60323232 T DE 60323232T DE 60323232 D1 DE60323232 D1 DE 60323232D1
Authority
DE
Germany
Prior art keywords
electronic circuit
nodes
test
selection
verifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60323232T
Other languages
English (en)
Inventor
De Logt Leon M Van
Jong Franciscus G De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60323232D1 publication Critical patent/DE60323232D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
DE60323232T 2002-07-08 2003-06-20 Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen Expired - Lifetime DE60323232D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02077733 2002-07-08
PCT/IB2003/002957 WO2004005946A2 (en) 2002-07-08 2003-06-20 Electronic circuit with test unit for testing interconnects

Publications (1)

Publication Number Publication Date
DE60323232D1 true DE60323232D1 (de) 2008-10-09

Family

ID=30011175

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60323232T Expired - Lifetime DE60323232D1 (de) 2002-07-08 2003-06-20 Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen

Country Status (9)

Country Link
US (1) US7199573B2 (de)
EP (1) EP1521974B1 (de)
JP (1) JP4176716B2 (de)
CN (1) CN100401086C (de)
AT (1) ATE406582T1 (de)
AU (1) AU2003244975A1 (de)
DE (1) DE60323232D1 (de)
TW (1) TWI287638B (de)
WO (1) WO2004005946A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7567521B2 (en) * 2006-06-06 2009-07-28 Litepoint Corp. Apparatus for capturing multiple data packets in a data signal for analysis
US20090021383A1 (en) * 2007-07-16 2009-01-22 International Business Machines Corporation Method for redundant control of service indicator leds
JP4365433B2 (ja) * 2007-09-11 2009-11-18 Ｏｋｉセミコンダクタ株式会社 半導体集積回路
US7928755B2 (en) * 2008-02-21 2011-04-19 Verigy (Singapore) Pte. Ltd. Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
US4575648A (en) * 1983-12-23 1986-03-11 At&T Bell Laboratories Complementary field effect transistor EXCLUSIVE OR logic gates
US4789951A (en) * 1986-05-16 1988-12-06 Advanced Micro Devices, Inc. Programmable array logic cell
JPS635272A (ja) * 1986-06-25 1988-01-11 Fujitsu Ten Ltd 出力異常検出機能付きロジツク回路装置
EP0400179B1 (de) * 1989-05-31 1995-07-19 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum internen Paralleltest von Halbleiterspeichern
GB2244364B (en) * 1990-05-24 1994-03-09 Coin Controls Coin discrimination apparatus
US5241265A (en) * 1992-03-26 1993-08-31 Northern Telecom Limited Logic function circuit with an array of data stores and their circuit testing
JP3865828B2 (ja) * 1995-11-28 2007-01-10 株式会社ルネサステクノロジ 半導体記憶装置
JPH10303737A (ja) * 1997-04-23 1998-11-13 Mitsubishi Electric Corp ３入力排他的否定論理和回路
US6622108B1 (en) * 1998-02-02 2003-09-16 Koninklijke Philips Electronics N.V. Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
JP4044663B2 (ja) * 1998-02-25 2008-02-06 富士通株式会社 半導体装置
DE10066260B4 (de) 1999-04-30 2013-11-14 Fujitsu Semiconductor Ltd. Halbleiter-Speicheranordnung, Leiterplatte, auf welcher eine Halbleiter-Speicheranordnung montiert ist, und Verfahren zum Testen der Zwischenverbindung zwischen einer Halbleiter-Speicheranordnung und einer Leiterplatte
TW444127B (en) * 1999-08-20 2001-07-01 Taiwan Semiconductor Mfg Comparing circuit, testing circuit and testing method for the parallel test of DRAM devices

Also Published As

Publication number Publication date
ATE406582T1 (de) 2008-09-15
TWI287638B (en) 2007-10-01
CN1666110A (zh) 2005-09-07
US20060061376A1 (en) 2006-03-23
WO2004005946A2 (en) 2004-01-15
TW200403444A (en) 2004-03-01
US7199573B2 (en) 2007-04-03
WO2004005946A3 (en) 2004-06-03
CN100401086C (zh) 2008-07-09
EP1521974A2 (de) 2005-04-13
AU2003244975A1 (en) 2004-01-23
EP1521974B1 (de) 2008-08-27
AU2003244975A8 (en) 2004-01-23
JP4176716B2 (ja) 2008-11-05
JP2005532548A (ja) 2005-10-27

Similar Documents

Publication Publication Date Title
KR0156547B1 (ko) 집적 회로용 검사셀
US6665828B1 (en) Globally distributed scan blocks
US6029261A (en) Test circuit and system for interconnect testing of high-level packages
ATE347112T1 (de) Testen von integrierten schaltungen
US6347387B1 (en) Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links
US4980889A (en) Multi-mode testing systems
KR890005534A (ko) Lsi/vlsi 검사 시스템용 분산 의사 무작위 순차 제어 시스템
US6349398B1 (en) Method and apparatus for partial-scan built-in self test logic
Soden et al. I/sub DDQ/testing and defect classes-A tutorial
US6275081B1 (en) Gated clock flip-flops
DE60323232D1 (de) Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen
KR20030075160A (ko) 입출력 도통 테스트 모드 회로
JPH116867A (ja) 多目的テスト・チップ入力／出力回路
US6986087B2 (en) Method and apparatus for improving testability of I/O driver/receivers
JP2000162284A (ja) 半導体集積回路
JP2008508541A (ja) 回路相互接続試験の構成とその手法
Kerkhoff et al. Detection of intermittent resistive faults in electronic systems based on the mixed-signal boundary-scan standard
CA1201815A (en) Reciprocal quiescence design method and apparatus
Jha et al. Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring
Masaki et al. Design aspects of VLSI for computer logic
CA1296110C (en) Reconfigurable register bit-slice for self-test
JPH032577A (ja) 試験回路
Sharma et al. Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards
US7131043B1 (en) Automatic testing for programmable networks of control signals
Nayana et al. Modified low power STUMPS architecture

Legal Events

Date Code Title Description
8364 No opposition during term of opposition