DE60321498D1 - Gegen Temperatur-, Spannungs- und Herstellungsschwankungen kompensierte Logikschaltung - Google Patents

Gegen Temperatur-, Spannungs- und Herstellungsschwankungen kompensierte Logikschaltung

Info

Publication number
DE60321498D1
DE60321498D1 DE60321498T DE60321498T DE60321498D1 DE 60321498 D1 DE60321498 D1 DE 60321498D1 DE 60321498 T DE60321498 T DE 60321498T DE 60321498 T DE60321498 T DE 60321498T DE 60321498 D1 DE60321498 D1 DE 60321498D1
Authority
DE
Germany
Prior art keywords
compensated
voltage
temperature
logic circuit
manufacturing variations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60321498T
Other languages
English (en)
Inventor
Janardhanan S Ajit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60321498D1 publication Critical patent/DE60321498D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60321498T 2002-03-01 2003-03-03 Gegen Temperatur-, Spannungs- und Herstellungsschwankungen kompensierte Logikschaltung Expired - Lifetime DE60321498D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36103302P 2002-03-01 2002-03-01
US10/293,259 US6985014B2 (en) 2002-03-01 2002-11-14 System and method for compensating for the effects of process, voltage, and temperature variations in a circuit

Publications (1)

Publication Number Publication Date
DE60321498D1 true DE60321498D1 (de) 2008-07-24

Family

ID=27737213

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60321498T Expired - Lifetime DE60321498D1 (de) 2002-03-01 2003-03-03 Gegen Temperatur-, Spannungs- und Herstellungsschwankungen kompensierte Logikschaltung

Country Status (3)

Country Link
US (2) US6985014B2 (de)
EP (1) EP1341307B1 (de)
DE (1) DE60321498D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7116129B2 (en) * 2004-07-20 2006-10-03 Micron Technology, Inc. Temperature-compensated output buffer method and circuit
US7157932B2 (en) 2004-11-30 2007-01-02 Agere Systems Inc. Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations
KR100706576B1 (ko) * 2005-08-01 2007-04-13 삼성전자주식회사 슬루율이 제어된 출력 구동회로
US7466601B2 (en) * 2006-12-01 2008-12-16 Qimonda Ag Output driver
US7923868B2 (en) * 2007-02-06 2011-04-12 Agere Systems Inc. Method and apparatus for adjusting a power supply of an integrated circuit
TWI331848B (en) * 2007-04-02 2010-10-11 Etron Technology Inc Inverter, nand gate, and nor gate with adjustable threshold and irrelative to voltage, temperature, and process
US20120162121A1 (en) * 2010-12-22 2012-06-28 Shih Chang Chang Slew rate and shunting control separation

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2744209C2 (de) 1977-09-30 1985-09-05 Siemens AG, 1000 Berlin und 8000 München Integrierte Schaltungsanordnung zur Ableitung einer zwischen zwei Pegeln umschaltbaren Ausgangsspannung
US4170740A (en) * 1978-02-24 1979-10-09 International Telephone And Telegraph Corporation High voltage switch and capacitive drive
US4216388A (en) * 1978-08-07 1980-08-05 Rca Corporation Narrow pulse eliminator
US4772812A (en) * 1981-07-27 1988-09-20 Data General Corporation Tri-state output buffer circuit including a capacitor and dynamic depletion mode switching device
JPS61191114A (ja) * 1985-02-19 1986-08-25 Nec Corp パルス発生回路
US5107139A (en) * 1990-03-30 1992-04-21 Texas Instruments Incorporated On-chip transient event detector
US5561393A (en) * 1992-02-03 1996-10-01 Fuji Electric Co., Ltd. Control device of semiconductor power device
US5334888A (en) * 1993-04-19 1994-08-02 Intel Corporation Fast exclusive-or and exclusive-nor gates
DE4400872A1 (de) * 1994-01-14 1995-07-20 Philips Patentverwaltung Ausgangstreiberschaltung
JPH0993118A (ja) * 1995-09-22 1997-04-04 Kawasaki Steel Corp パストランジスタ論理回路
US5736888A (en) * 1995-12-20 1998-04-07 Advanced Micro Devices, Inc. Capacitance elimination circuit which provides current to a node in a circuit to eliminate the effect of parasitic capacitance at the node
JP3017133B2 (ja) * 1997-06-26 2000-03-06 日本電気アイシーマイコンシステム株式会社 レベルシフタ回路
US5945850A (en) * 1997-11-03 1999-08-31 Lucent Technologies Inc. Edge signal restoration circuit and method
US6353349B1 (en) * 1998-06-22 2002-03-05 Integrated Silicon Solution Incorporated Pulse delay circuit with stable delay
US6222413B1 (en) * 1999-03-16 2001-04-24 International Business Machines Corporation Receiver assisted net driver circuit
US6351138B1 (en) * 2001-03-22 2002-02-26 Pericom Semiconductor Corp. Zero-DC-power active termination with CMOS overshoot and undershoot clamps
US6545520B2 (en) * 2001-03-28 2003-04-08 Intel Corporation Method and apparatus for electro-static discharge protection
US6653878B2 (en) * 2001-09-24 2003-11-25 Microchip Technology Inc. Low-power output controlled circuit
US6590430B2 (en) * 2001-10-09 2003-07-08 Thomson Licensing, S.A. Dual use of an integrated circuit pin and the switching of signals at said pin

Also Published As

Publication number Publication date
US20030164722A1 (en) 2003-09-04
US6985014B2 (en) 2006-01-10
EP1341307B1 (de) 2008-06-11
US7268595B2 (en) 2007-09-11
EP1341307A1 (de) 2003-09-03
US20060114037A1 (en) 2006-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M